Forum Post: RE: Stopping and re-starting McASP Tx/Rx DMAs using EDMA3
Some more bits of informationI am using Slot 0 in both TDM and SPDIF modes. So, checking for XDATA clearing should be fine according to Section 25.2.4.1.2 of OMAP-L138 TRM, I am guessing.I could...
View ArticleForum Post: RE: Could not write to L1P SRAM
Chad,I configured upp registers as below, and used the TSCL register of CPU for testing each register read/write access.Actually, I didn't configure the IDMA for CPU at all, so the mode of IDMA is...
View ArticleForum Post: RE: Global variable maintaining coherence in multicore program...
Hi Kaka,Can you provide a complete reproduction code in a CCS project we run on C6678 EVM?On the other hand, to isolate your issue,By completely disabling cache (L1D and L2), do you still see the same...
View ArticleForum Post: RE: C6678 Cache for L2SRAM
Hi Yuchao,To my best knowledge, in CC678 whenever L1D is enabled, L1D and L2 are kept coherent.However it does not mean you never see inconsistency between L1D and L2 at "a moment." We have a chance...
View ArticleForum Post: trouble in AlgLink_algProcessData()
i want to change the data in OSD, so that i can develop my own Algorithm,but i failed , my code is :Sw_osd_ti_alg.c AlgLink_algProcessData(AlgLink_Obj *...
View ArticleForum Post: RE: Utils_memAlloc_cached() cost too much time
Hi,Badri Narayananwhat's the difference between Utils_memAlloc and Utils_memAlloc_cached?It seems the difference is as the name mean,memory alloc by Utils_memAlloc_cached are cached.but the code of...
View ArticleForum Post: RE: The problem for PC to access C6678
Hi Yuchao,I don't think it's a cache coherency issue of C6678... My understanding is that L1D and L2 are kept coherent whenever L1D is enabled.> PC write some parameters in C6678's L2SRAM,and make...
View ArticleForum Post: Modifying ti8148 Ezsdk to use MII instead of (R)GMII
hello, all!In my customer board, I use the DP83848i chip work in MII mode(100M speed). and I check that in the make menuconfig, there are some menus to config mode like:[ ] Ethernet(10 or...
View ArticleForum Post: RE: FVID2 driver usage on DM385 IPNC RDK 3.5
As long as you add each command with different identifier (i.e. ISS_SENSOR_IOCTL_BASE + 0x10) I think you can add any number of IOCTLs.RegardsRajat
View ArticleForum Post: RE: DM648 NOR BOOT issue
How did you change the flashutil and solve the problem? Now I am in the same situation, I burn the UBL and APP into the flash, then power up the board, the UBL could run rightly, but the APP program...
View ArticleForum Post: RE: DM648 flash erase and write
Now I run into the same problem, the flash erasing is usually failed. The flash chip is the same as the EVM's.zhu
View ArticleForum Post: RE: how to install arago file system ?
sir i have to Boot uImage with NFS filesystem. and than i have to mount ubifs in my device..but I dont know howto.
View ArticleForum Post: RE: DM648 ubl BOOT
Now if the DM648 ubl expert is still on vacation, I am run into the same question. The bootcfg pins are all right and the bootcfg reg is also right. After the flash burning is completed, power up the...
View ArticleForum Post: RE: EVM DM648 boot mode issue
Mark, how did you solve the problem? now I am in the same question. The UBL can run but the app could not run.zhu
View ArticleForum Post: RE: Problem about DM8168 video display time delay
Hello Badri:today i changed the displayPrm->queueInISRFlag = TRUE;And i use vcap_vdis demo to test, only 1chan connect with PAL video input,It do works,the follow is logs: [m3vpss ] *** [SWMS1]...
View ArticleForum Post: RE: Errors in EDMA Data Transfer
Hello Chad,Can you explain the meaning of parameter of CSL_Edma3ParamSetup. I don't know what it is use to do in the follow code: CSL_Edma3ParamSetup myParamSetup; myParamSetup.srcAddr...
View ArticleForum Post: RE: DM8148 HWIs
Hi,Also - I didn't see HWI module in Sys Bios document, but it does mention "Hwi_create" function:[quote]3.3.1 Creating Hwi ObjectsHwi_Handle hwi0;Hwi_Params hwiParams;Error_Block...
View ArticleForum Post: RE: question about OMAP L137(L138)
No expert on this. Some comments from personal experience. On the OMAP-L137, ROM bootloader loads and runs the DSP bootloader. The DSP bootloader loads and starts the ARM bootloader. So the DSP can...
View ArticleForum Post: RE: DDR3 SW Leveling
HiThe UBOOT code is correct and this is because - Data macros are connected to byte lanes in the reverse order by design..meaning Data macro 0 controls bytelane 3 and datamacro3 controls bytelane0 and...
View ArticleForum Post: Can we get the MPS430 source code on EVMDM648?
Nowadays, I am testing my dm648 board. When I burn the UBL and App program into flash, power up, the UBL can run but the App could not run. And I debug the UBL, it can copy the App code into DDR, and...
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