Chad,
I configured upp registers as below, and used the TSCL register of CPU for testing each register read/write access.
Actually, I didn't configure the IDMA for CPU at all, so the mode of IDMA is default I think.
typedef struct {
volatile UINT32 ACT: 1;
volatile UINT32 PEND: 1;
volatile UINT32 r3_2: 2;
volatile UINT32 WM: 4;
volatile UINT32 r31_8: 24;
}UPS2_BITS;
typedef union {
volatile UINT32 ALL;
volatile UPS2_BITS BITS;
}UPS2_REG; // I,Q
#define UPP_LoadDescriptor2DMAI_vo(DataPtr, LineCnt, BytesPerLine, LineIndex) \
uppregs->UPID0 = (UINT32)( DataPtr ); \
uppregs->UPID1.ALL = (UINT32)((LineCnt)<<16 | (BytesPerLine)); \
uppregs->UPID2.ALL = (UINT32)( LineIndex );
void upp_write()
{
/* clear DMA status for new transmit */
uppregs->UPIER.ALL = 0x00001F1F; // 15 cycles
/* check if DMA I is pending */
while (uppregs->UPIS2.BITS.PEND) {} // 120 cycles
/* send packet */ // 20 cycles
UPP_LoadDescriptor2DMAI_vo((void *)tx_pstg, 1U, BUFFER_SIZE, BUFFER_SIZE);
while (uppregs->UPIS2.BITS.ACT == 0) {}
}
I found that it costed almost 120 cycles to check the bit of pend. So the bit of ACT was.
Q: Is it cost more cycles when access bit field instead of 32 bit register?