Hi Yuchao,
To my best knowledge, in CC678 whenever L1D is enabled, L1D and L2 are kept coherent.
However it does not mean you never see inconsistency between L1D and L2 at "a moment." We have a chance to see an L1D dirty cache line (modified but not reflected to L2). However, it does not matter. C66 cache coherence mechanism ensures that a core-outside DMA master sees the modified data in L1D because L2 inquires (or snoops) L1D if it has a dirty line on the accessed address. If L1D has a dirty line, the data are forwarded to L2 controller and the outside DMA master finally reads the modified data. (In other words, the coherency is kept.)
Regarding the cache coherency between L2 and L3, the http://www.ti.com/litv/pdf/spry150a (KeyStone memory
architecture) is helpful.
Regards,
Atsushi