Hi Yuchao,
I don't think it's a cache coherency issue of C6678... My understanding is that L1D and L2 are kept coherent whenever L1D is enabled.
> PC write some parameters in C6678's L2SRAM,and make sure it has been finished by reading it back.
Is the readback from PC actually accessing PCIe? Is the variable declared as 'volatile' if coded by C language?
Do you see improvement by setting the RELAXED field to zero in the DEV_STAT_CTRL (in the PCI Express Capabilities Registers) of C6678?
Regards,
Atsushi