Forum Post: RE: Facing issue in Interlaced encoding with EzSDK on DM814x...
Hitesh has already concluded saying that the issue is with capture device and not encoder HW/SW. And the same was even said by Ram in earlier replies. So now we will have to look more into capture HW...
View ArticleForum Post: RE: How to get Linux framebuffer fully displayed on an interlaced...
[quote user="Badri Narayanan"]Pls explain your data flow for video and the changes you did to display full video frame when showing 1080i60 in displayLink. Also mention what changes you did to the grpx...
View ArticleForum Post: With the CE development, DM6446. We first use of G711DEC...
With the CE development, DM6446. We first use of G711DEC routines, bringing in the DVSDK G711 all of the code. Using CCS5.3 compiler generates the lib files. Then using genpackage and genserver wizard...
View ArticleForum Post: RE: C6678 HyperLink Debugging
No interrupts occur. I'm able to write DSP HyperLink registers remotely from the FPGA.
View ArticleForum Post: RE: Global variable maintaining coherence in multicore program...
Kaka,> [1] My project is a real-time wireless signal process system, so, disabling L1d and L2 cache is not a good solution.I'm suggesting for only isolation purpose. Not for your final design.>...
View ArticleForum Post: RE: Problem about DM8168 video display time delay
Thank you for tell the deinterlace problem, i will add nsf link laterand the log will share with you later
View ArticleForum Post: Can Dm8168 support external sync video display
Hi all:Here I have question about that Can Dm8168 support external sync video display,I see the external sync video display option in dvr_rdk 3.50, but i do not find input display pin to...
View ArticleForum Post: RE: Availability of reference source code for DM368
Steinar,The current working model is that you need to first buy one reference design from the reference design partner Appro (www.appropho.com). Once you buy one reference camera the software release...
View ArticleForum Post: RE: About the useage of EDMA in DM8127
Hi,The destnation memory may be cached.Can you print the address of 'frame_buffer' and also send me your '../ipnc_rdk/ipnc_mcfw/mcfw/src_bios6/cfg/ti814x/FC_RMAN_IRES_c6xdsp.cfg' file?Pl. do cache...
View ArticleForum Post: RE: OMX DEI x/y offset not working correctly
Hi Steven,When runtime updates happen, VFPC component is checking for change in resolution wrt to previous setting.Hence we you just change startX, startY, component won't interpret unless there is...
View ArticleForum Post: RE: About IBL for C6670
Hi,g.f.You don't need to implement I2C. You can boot from spi directly.Here is a reference link. I hope I can help a...
View ArticleForum Post: RE: question about c6678 SRIO LSU
Hi,My interpretation of the manual is that "shadow register" is composed of a full set of REG0-REG5, so a transaction consume only one shadow register (set).From SPRUGW1A, §2-3.1[quote]Each shadow...
View ArticleForum Post: Question about VPIF of DM6467
Hi,I have a sync issue that VBI line is shown on a monitor sometimes and I doubt the capture side because we’ve seen abnormal number of hsync in camera sometimes. But currently, there is no error...
View ArticleForum Post: RE: venc-secondary stream?
No such a feature is not supported. The h264 encoder in DVR RDK supports SVC-T which means same stream can have multiple layers with each layer having lower FPS but all have the same resolution.
View ArticleForum Post: RE: I want to create a dual enocder path in...
Hi Krunal,Capture component will have only one output port. Hence it is not possible to for you to use same input.also Encoder expects 420SP as input always.Ram
View ArticleForum Post: RE: Utils_memAlloc_cached() cost too much time
The difference between the two functions is the heap used to allocate memorygUtils_heapMemHandle[UTILS_MEM_VID_BITS_BUF_HEAP] is placed in cacheable memory...
View ArticleForum Post: RE: DM8127 encode link stop due to no output buffer
Hi Rajat,All previous results are build in the release mode already.How to increase the size of bit buffer pool? Just manually edit the source code of "UTILS_ENCDEC_GET_BITBUF_SIZE"? I have try to...
View ArticleForum Post: RE: Problem about DVRRDK 4.0
Hi,The NVR GUI app can be run on a 1GB DDR board with 256MB Linux although with lesser number of Channels.We have not tried this yet, but we could try this out and let you know how many channels can be...
View ArticleForum Post: H.264 rate-control encoding simulate VBR as CBR
Hi all,we are working on the DM8168 wth the RDK 4.0, and since we can't use CBR at H.264 encoder at interlace mode, we wish to use the VBR algorithm, my questions are:what are the main paramters that...
View ArticleForum Post: RE: Why C6657 Ethernet interface speed is very slow(100kbps)?
Hi Xiaogang,How did you measure the speed? I guess the debug code is not optimized for speed.Regards,Atsushi
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