Forum Post: RE: configuration request type1 PCIe C6678
Hello,just to give you more explanation, I configured the register GFC_SETUP in RC side:cfgTrans.bus = 3;cfgTrans.device = 0;cfgTrans.func = 0;cfgTrans.type = 1;BDF=3:0:0 for the EP1, and I send Type1...
View ArticleForum Post: RE: OMAP-L138 C6748 USB0
Hi Rex,[quote user="Rex says"] I believe after the connect the next step is to reset the peripheral by pulling down the D+,D- lines. Is this correct and how do I do it? [/quote]yes, correct the next...
View ArticleForum Post: RE: Help: one of our AM1810 developing board cannot work
Hi！Even, Any no junks print out on serial ? Yes，but only 00 was printed out after powering on or pushing reset button. In the attached file here-TPS6507xEVM user guidance, at page 19, BOM list,...
View ArticleForum Post: RE: help for my simple code/ Use of switches
Hi,The following code will demonstrate the GPIOs for LEDs and SWITCHEs.Switches -> DIP switch Sw1[5:8]LEDs -> D4,D5,D6,D7/** * \file gpio_flip.c * * \brief This is a sample application file...
View ArticleForum Post: RE: C6678 TSIP interface loopback
Hi,1. No.2. In LLB(Link Loop Back) test configuration, the receive DRx outputs are internally connected to the corresponding transmit DXx inputs. So the transmit and receive data will not be latched in...
View ArticleForum Post: RE: Question about McFW link in/out frame format in dvrrdk4.0!!
That change cannot cause such an error . It looks like you have modified the swms nextLink from display to something else. I doubt you have done the changes correctly as the chanegs in the post are...
View ArticleForum Post: RE: how can we read and write into EMIF?
Rakesh,FYI, the SN74LVCH16245A is not a latch because it does not retain a pin's value after some latch condition is met. This device is a simple bus transceiver.What is the 20 pin connector you are...
View ArticleForum Post: RE: EVMK2H using materials
Hi Jie,Please refer below link for Keystone II device architecture.http://processors.wiki.ti.com/index.php/Keystone_II_Device_ArchitecturePlease find the datasheet and all the technical documents in TI...
View ArticleForum Post: dm8148 edma
I am working on the Dm8148 mistral EVM . Trying to write a driver that activate the mcAsp + Edma from the c674x without success . The dma does not take care of mcAsp events . Does the Dma have...
View ArticleForum Post: RE: Problem with EVMK2H Powerup in MicroTCA Chassis
Hi Brandy,Thank you. The board referenced in that link is a Keystone I architecture. I am told that the the EVMK2H, which is Keystone II, does not use the same MSP430 MMC and the MMC firmware will not...
View ArticleForum Post: RE: Procedure to run vpif_lcd_loopback in starterware
Rohit,Please check the Bootloader App Note to find all of the available boot modes. For Emulation mode, you set all 4 switches to 1, which I think means 'off'. I wish the schematic or Getting Started...
View ArticleForum Post: RE: How change Outbuf's size?
Hi Ritesh: Yes,! But when buff_size isUTILS_SCD_OUTBUF_SIZE(), all is ok. Why?
View ArticleForum Post: The left and right audio channels are exchanged!!
Dear Sir,We have a serious problem with OMAP-L137. After the Linux is booted, we run the following commandarecord -d 20 -D 'hw:0,0' -r 96000 -f S32_LE -c 2 | aplay -D 'hw:0,0' -c 2and feed the left...
View ArticleForum Post: RE: Output FPS setting on swMs
Pls modify /dvr_rdk/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.cSwMsLink_drvGetTimerPeriod() if (layoutParams->outputFPS == 0 || layoutParams->outputFPS > 200) {...
View ArticleForum Post: RE: omapl138 large latency when dma reads uart rx
Hi!1) The UART FIFO reports reception of data upon completion of a programmable number of chars (register IIR/FCR). What is your byte number threshold? Try to lower the threshold. 2) How do you measure...
View ArticleForum Post: RE: Video is not smooth due to swMs' fps setting
1.Use the SYSTEM_SW_MS_LINK_CMD_SET_FRAME_RATE to set the correct input and output fps rate required.This will result in swms dropping input frames at equal interval.2. When connected to display enable...
View ArticleForum Post: RE: DM814xevm M3 core UART with DMA
Enabling cache on M3(media controller) core solved this issue.I Do not know the reason.may be problem got hidden:) Thanks every one.
View ArticleForum Post: RE: Video Compression
Roberto,In my search instructions, I mentioned "near the top" of the list. You appear to have only looked at the one item at the top of the list. The TI.com search capability is very thorough and...
View ArticleForum Post: SPI0 CLK continuously enable
Hi All!I need generate clock for external ADC by my L138-target. Each of timer output pins is already busy, toggle GPIO in the timer interrupt - bad idea, because of big jitter in this case.I want to...
View ArticleForum Post: RE: problem C6000 ver 7.2.0
(Please visit the site to view this file)(Please visit the site to view this file)Daer RajasekaranAt first thanks fpr your cooperation !!Ok I am working with DSP TMS320C6748 device .I att you files...
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