Forum Post: RE: C6678 TSIP interface loopback

Hi,

1. No.

2. In LLB(Link Loop Back) test configuration, the receive DRx outputs are internally connected to the corresponding transmit DXx inputs. So the transmit and receive data will not be latched in registers/memory.

3. It is possible in DLB mode(Data Loop Back). "Successful operation is determined by comparing a receive frame buffer in memory with the corresponding transmit frame buffer in memory."

Thanks.