Forum Post: RE: Error 600 DSP C5000
Have you checked out this forum posting? I think your problem is related.Regards.
View ArticleForum Post: RE: C6678 SGMII CDR Configuration
Daisuke,Will this help? http://www.ti.com/lit/an/sprabc1/sprabc1.pdf, section 8.2.5?Regards, Eric
View ArticleForum Post: UL RADT and PS data
Hi,I have a question about UL timing in case of LTE system. Referring to AIF2 interface, if the ULRADT timer is programmed with a timing advance from the reference RADT, the Symbol number attached in...
View ArticleForum Post: bandwidth limitations with HyperLink on the EVM
I have a customer trying to connect two EVMs to test hyperlink. He is asking what is the maximun bandwidth that can be supported in this configuration. He understand that this is to demo the...
View ArticleForum Post: RE: HELP ME PLEASE !!
There is a link to CCS4 download. You can try that. Some warning messages are ok to ignore. You have to decide.Are you aware that you can only access MSP430 on ACTBP via JTAG? The C5535 DSP is not...
View ArticleForum Post: RE: Looking for low power audio dsp chip
You can check out the C55xx family of products.Regards.
View ArticleForum Post: RE: Starting digital signal processing with TMS320C6713 DSP...
Yes they do comprise XSpice, footprints for PCB layout and 3D models which can be imported into ANSYS or other FEA tools for thermal and EMC analysis. But all in all, it is beyond my knowledge....
View ArticleForum Post: RE: Questions about implementing local reset across PCIe bus (C6670)
Useful info which I found in another post (http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/253724.aspx):DSP_BOOT_ADDRn will hold the 22 MSBs (bits31-10) of the CorePac boot address. bits9-0...
View ArticleForum Post: RE: questions about L1D, MAR and cache coherence on C6657
Hi Weichun,The cache coherence operations on L1D are only required if DMA/Other writes code to L2 SRAM or CORE modifies code in L2 SRAM. In your use case, do you have any DMA activity from DDR to L2 ?...
View ArticleForum Post: AM3874/DM8148 HDVPSS fails on its firmware loading after a...
Hello,We have enabled the watchdog timer on the AM3874 for our board. Upon testing it where the watchdog reset occurs, we encountered an issue where the AM3874’s HDPVSS module is unable to properly...
View ArticleForum Post: How to configure AM3874 to use the highest CPU frequency for both...
Hello,We are using both the 800MHz and 1GHz version of the AM3874 on our boards. I am trying to follow the TI forum post to configure the AM3874 to its highest capable CPU frequency by changing...
View ArticleForum Post: RE: "Multi-Pass" FFT using DSPF_sp_fftSPxSP API.
Hi Kawada,Yes, This appears to be a documentation issue and the loop that you have highlighted in your first post is the right way to implement the multipass. If you look at the earlier example in the...
View ArticleForum Post: RE: C5535 Bootloading from SPI flash with 2 images at different...
[quote user="Ron"]Basically I would be copying words from SPI flash to RAM[/quote]Correct. [quote user="Ron"]how do I give control to the new loaded program then ?[/quote]Usually this is done by the...
View ArticleForum Post: Pipeline Runs At Half Resolution, Hangs At Full Resolution
The following pipeline is intended to simulate capturing two streams, mixing them picture-in-picture, muxing in audio and writing the result to a file: hres=960 vres=544 hres2=`expr $hres / 2`...
View ArticleForum Post: C6678 EDMA0 parallel transfer
hi：I am using C6678 EDMA0, and I make 8 cores to use 8 shadow regions each other with different channel and param, then I use Manually-Triggered way to transfer together 8 cores（group all cores）. When...
View ArticleForum Post: RE: Query regarding running Android on DM814X using DVR-RDK
DVR RDK is entirely user space code so there isn't much effort to port to Android if you already have EZSDK functional. Only posix phtread APIs are used by dvr rdk library code.From getting a full DVR...
View ArticleForum Post: RE: LCD backlight control using PWM/CAP pin in OMAP L138/AM18XX
Hi Sivaraj,Please find the below pinmux configured registers/*******************/ MUX_CFG(DA850, ECAP0_APWM0, 2, 28, 15, 2, false) /* eCAP1 function */ MUX_CFG(DA850, ECAP1_APWM1, 1, 28, 15, 4, false)...
View ArticleForum Post: USIM Interface Configuration
Hi,I would like to know if there is a detailed specification about USIM Interface.Regards,Paresh
View ArticleForum Post: RE: about set vip parameters dynamically
You have to delete and create the FVID2 capture driver as VIP configuration is a driver create param.This also means you will have to delete and create the capture link.This requires deletion and...
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