Hi Weichun,
The cache coherence operations on L1D are only required if DMA/Other writes code to L2 SRAM or CORE modifies code in L2 SRAM. In your use case, do you have any DMA activity from DDR to L2 ?
Regards,
Rahul
PS: Please also look at the scenarios described in L2 and L1 Cache coherency sections of the C66x Cache user guide.