Forum Post: RE: SMPTE 296
Hi Vaishak,The SMPTE 296 M mode requires the same clock control for the VPIF module as in BT.656 and BT.1120modes. The video input clock source is 74.25 MHZ.Please refer Table 36-8 page no 1766 in the...
View ArticleForum Post: Kernel does not start after upgrading keystone U-Boot
Note: This is with K2 EVM 1.1I've been using a version of the keystone U-Boot I grabbed around June 2013 (around the time of MCSDK mcsdk_linux_3_00_00_11) along with the ./images from a newer version...
View ArticleForum Post: RE: C Concatenation Operator (##) Error
I figured it out. The expansion worked differently than I expected.I made the following changes to my macros: #define CSL_FINST(reg, PER_REG_FIELD, TOKEN) \ CSL_FINS((reg), ##PER_REG_FIELD,...
View ArticleForum Post: RE: CSL Libraries and Bitwise C code
Thank you, this is exactly what i was looking for your interpertation was right on target the ebsr register is in the tech ref manual of the dsp5535 and it explains it pretty well.I'mpretty familiar...
View ArticleForum Post: RE: question about C6747 Ref. Schematic
Hi Debin,Basically TI devices (OMAP-L137) that utilize an ARM core that requires Adaptive Clocking support an RTCK pin. RTCK is used by the XDS (if it supports Adaptive Clocking) to gate TCK until the...
View ArticleForum Post: Comments need on I2C spru877e
There are beautiful schemas in document about I2C module of C672x.For example Figure 18 on page 26.What means box "Reprogram the MMRs"?The text "Reprogram the MMRs" is only on schemas and not explained...
View ArticleForum Post: RE: Img_dilate_bin function not working as expected.
Vikas,Are you setting the size of output same as input image array?RegardsYogesh
View ArticleForum Post: 66AK2H12 smartreflex
The latest data manual for 66AK2H12 (rev E) says that the default Smartreflex (AVS) interface is '4pin 6-bit dual phase VCNTL', and shows timing diagram for this on pg 274 and 275. Is the '4pin 6-bit...
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Forum Post: OMAP-L138 ASLA and Codec Engine have a Conflict
Hi everyone,We have a problem when used OmapL138, We used ALSA to capture audio signal in one thread and run Audio_copy example in Codec Engine in another thread.My problem is that when I call...
View ArticleForum Post: Boot single image on multiple cores in TMS320C6678
Hi everybody,I have a single .out binary image and I want to run it into all the 8 cores of the TMS320C6678 from NOR flash (with the IBL in the I2C EEPROM).I used norwriter utility to write the binary...
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Forum Post: RE: 66AK2H12 smartreflex
Hi Scott,Section 10.2.4 of the data manual is incorrect. When connecting the 66AK2H12 in 4-pin 6-bit dual-phase mode, VCNTL[5:2] should be used as specified in Table 8-29. The figure below illustrates...
View ArticleForum Post: RE: decode_display_a8host_debug.xv5T ejects error -...
Hi! Thanks for prompt reply!I can't do "make install", because I did not configure my NFS and I use tftp!BTW, I executedslaveloader_release listand I get the following:Current status of slave...
View ArticleForum Post: On C66x CorePac Registers, MAR and MPAX
Hello everyone,(CCS 5.5, EVMC6678)On C6678 data manual there is the following memory map :Logical address start 01800000 end 01BFFFFF bytes 4M description C66x CorePac RegistersOn the CorePac User...
View ArticleForum Post: RE: Kernel panic on 6638 EVM for MCSDK 3_00_03_15
I had the same issue. It seems as though formatting the nand before burning the .ubi image worked for me. See my post here...
View ArticleForum Post: RE: Multicore message address is set to zero
Hi Julian,What's the size of the message in your application? Do you enough Heap for message Q?Is it possible you can simplify the code and just keep the IPC part and share your code?Xiaohui
View ArticleForum Post: RE: DM365 with new NAND (Samsung NAND 128MiB)
Unfortunately this does not fix my issue. When I start my application and I begin using the voice codec the operating system crash after few seconds. My code was tested before I rebuild the kernel and...
View ArticleForum Post: RE: 66AK2H12 documentation on RoHS needed
Hi Magnus,We’re sorry that the quality & environmental data portion of the 66AK2H12 webpage is not fully updated; it can take a year or more to fully validate FIT/DPPM for a new technology as full...
View ArticleForum Post: Boot problem for TiDSP C6452
Hi,i am getting a boot problem when we try to boot our C6452 DSP. its quite strange that it does not happen every time and also with same DSP. it occures some time only with some DSP's. And also we are...
View ArticleForum Post: OMAP3530 BT.656(PAL) alpha blending
Good day,I have the Tsunami base board from Technexion, with the OMAP3530 module (TAO-3530). The board is equipped with the tvp5146pf BT.656 decoder chip.At...
View ArticleForum Post: RE: C6657 SmartReflex Timing
Thanks, Bill.Assuming we boot off PCIe, can you narrow it down for us at all, if only in terms of where in the boot sequence?We would feel pretty safe aiming for a delay time somewhere in between the...
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