Forum Post: RE: question about the *.cfg file of JPEG2K Encoder on C66x
Hi Wang, j2e_ti_def.h is part of the the Library project, however, C66x_j2e_01_00_00_01_ELF published on the web doesn't include the source files for the codec library only the prebuild library...
View ArticleForum Post: RE: CSL Libraries and Bitwise C code
The ## operator is the C standard token-pasting operator. When a call to macro CSL_FINST is preprocessed, it will result in something that looks like this (assuming no further macros). This is...
View ArticleForum Post: RE: OMAPL-138: Synchronize all eCAP modules with SWSYNC
Hi All,Upon further investigation we found on a single eCAP0, if SYNCI_EN is 1 (ENABLE) setting the SWSYNC to 1 will result in the TSCTR loading the shadow register CTRPHS. However, that sync signal is...
View ArticleForum Post: RE: A question about using the lwIP TCP/IP stack on C6748
Dear Shankari,OK, I understand. I'll try it.Thanks for your reply and information! Regards,Oliver
View ArticleForum Post: optimizing C66x PCIe transfers for multiple cores
Vivek and other TI experts-With the quad 6678 PCIe card, we're using memcpy to/from host-mapped memory and DDR3 mem. Typically we get a rate of around 90 Mbyte/sec. However when code is running...
View ArticleForum Post: RE: Keystone I DDR3 Leveling Issue
Hi Tom,Thank you for your reply. I am grateful for your cooperation.Best regards,Daisuke
View ArticleForum Post: RE: boot log
hi Badri, ReshmaMay I know the reason about adding udelay(100)?
View ArticleForum Post: RE: network speed
hello Yogesh,thanks for your reply. You're a very really nice person much.Is there any other side effect except the reduced network bandwidth?
View ArticleForum Post: RE: how to display framebuffer to sd output(/dev/fb2), dvrrdk4.0,...
hi, badri, i _reverting_ the patch, and problem fix now .thank you!
View ArticleForum Post: RE: How many cores is needed to run H264HP Encoder with...
Hi Tsai our C66x H.264 HP encoder is multicore but not multichipThank you,Paula
View ArticleForum Post: RE: OMX failing to restart a scalar component on DM814x
Hi,Thanks for your reply, I've attached the debug log (using the loggerDump utility) for the scaler application (as described on my second post) since this involves just the component that Is giving...
View ArticleForum Post: RE: Hybrid OPP
Could you be more specific about not possible ? Does it mean not tested, tested and guaranteed to fail ? I have a board that runs just fine with the following setup :- ARM Freq is 800 MHz, DSP Freq is...
View ArticleForum Post: RE: EDMA:L2 to L2 succeeded, but L2 to DDR3 failed
Hi Feng,I meant the DSP part number, thanks for confirming. It is possible that isolated reads and writes may work even if leveling failed but it is best to assume nothing will work with full data...
View ArticleForum Post: RE: Triggering Shared Peripheral Interrupts of ARM Corepac from...
Please include the source files in the attachment to your project and call "INTH_InitHandler();" along with HWI setup to see if the peripheral event could trigger ARM GIC interrupt, such as...
View ArticleForum Post: RE: c6748, NDK, FLASH, BIOS6
(Please visit the site to view this file)Here's the project and AESconfig
View ArticleForum Post: RE: question about the *.cfg file of JPEG2K Encoder on C66x
Hi Wang,I was pointed out that EDMA3LLD doesn't support C6671 platform...
View ArticleForum Post: RE: C6654 DDR3 initialization problem
Tom,Thanks for sticking with this and helping with the debug process. We have a way we could do a two-stage boot process if necessary, we were just trying to avoid it if possible and use the RBL with...
View ArticleForum Post: RE: how to flash nand flash via Gel file and nand-flash-writer.out
Hi Renijth,here are your answeres:1. What is the size of the image that you are flashing? [vivek] i flashing uboot.noxip.bin which 208KBytes less then 255KB.2. Have you confirmed your DDR settings and...
View ArticleForum Post: Error with RTS Library on K2H Cortex-A15
I'm attempting to run some code on the Keystone II ARM processor and am running into an issue with the RTS library. Since CCS 5.5 doesn't seem to support the Cortex-A15 yet I'm compiling for a...
View Article