Hi Feng,
I meant the DSP part number, thanks for confirming. It is possible that isolated reads and writes may work even if leveling failed but it is best to assume nothing will work with full data integrity if it fails.
(1) When you say leveling failed, does it show a timeout on all three levelings?
(2) Are you following the initialization procedure recommended in the Keystone DDR3 initialization application note and plugged in the appropriate values in the PHY and register calculation spreadsheets?
(3) Have you verified that your layout complies with the guidelines in the DDR3 design requirements guide?
(4) How many boards do you have and how many show this behavior?
Note: If you have one, you can also verify if your program works as expected on the TI EVM.