Hi Biser, I build my Linux from poky tag "rocko-18.0.3" and meta-ti tag "ti2018.03" using Yocto build system. The Linux version is 4.14.67. Thank you!
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Forum Post: RE: Linux/BEAGLEBK: Changing PHY to Gigabit
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Forum Post: RE: TMDSDSK6416: Generate short pulse with DSP Timer
Dear Sahin, Thank you for your reply. My DSK board is version 3 and it runs at 1GHz. I have configured the timer at 1MHz and the input clock to the timer is 125 MHz. I toggled the timer in a simple while loop as you suggested and I got 80ns pulse widths. Timer should provide shorter pulse widths than this value. As the datasheet for the TMS320C6416T says, the timer is able to output 5ns pulse duration at high state. By the way, is there any way to change the DSP core frequency without using DSP/BIOS configuration? Best regards, Farzin
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Forum Post: RE: AM3352: Revision changed from Rev.J to K
Hello, Yes, closing the interface from a delay/setup/hold perspective is sufficient to ensure robustness.
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Forum Post: 66AK2G12: Minimum required pins of mmc/sd only for SD boot?
Part Number: 66AK2G12 Dear Champs, Could you please let me know which pins of mmc/sd are required at minimum only for SD boot? e.g. there is no plan to use SD card, but will use it only for SD boot. due to board size, my customer would like to connect minimum pins for SD boot. Thanks and Best Regards, SI.
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Forum Post: RTOS/PROCESSOR-SDK-AM65X: AM65xx IDK ADC
Part Number: PROCESSOR-SDK-AM65X Tool/software: TI-RTOS Hi, I was able to build the ADC example in the diag folder in the SDK. i have been trying to transplant the adc code from adc_AM65xx.c/.h into the ECAT PRU code (or any other project for that matter) but I keep running into the same runtime exception. Whenever i get to ADCGetRevisionId(baseAddress, &revId); it will crash with this output in the CIO. I'm not entirely sure what I'm missing. Reading other post about ADC it sounds like maybe my pinmux is wrong? or maybe my MMU is not setup properly? Not sure what i'm looking for to fix this issue. [CortexA53_0_0] = 0x00000000700188d0 X3 = 0x000000007006e608 X4 = 0x000000007006e608 X5 = 0x000000000006e608 X6 = 0x000000007006e610 X7 = 0x0000000000000000 X8 = 0x0000000000000023 X9 = 0x0000000000000001 X10 = 0x0000000000000001 X11 = 0x0000000000000000 X12 = 0x0000000000000bd0 X13 = 0x0000000000000000 X14 = 0x0000000000000013 X15 = 0x00000000000000d1 X16 = 0x000000000000003a X17 = 0x0000000000400234 X18 = 0x0000000000000037 X19 = 0xffffffffffffffff X20 = 0xffffffffffffffff X21 = 0xffffffffffffffff X22 = 0xffffffffffffffff X23 = 0xffffffffffffffff X24 = 0xffffffffffffffff X25 = 0xffffffffffffffff X26 = 0xffffffffffffffff X27 = 0xffffffffffffffff X28 = 0xffffffffffffffff X29 = 0x0000000070077740 X30 = 0x0000000000000000 SP = 0x0000000070077740 ELR = 0x000000007002efc4 ESR = 0x96000006 SPSR = 0x40000344 Data Abort: PC = 0x000000007002efc4 LR = 0x0000000000000000 ti. sysbios .family.arm.gicv3.Hwi: line 1140: E_exception: A hardware exception has occurred. xdc.runtime.Error.raise: terminating execution Thank you, Steven
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Forum Post: AM5728: question on TSHUT
Part Number: AM5728 I've seen several posts on the behavior and usage of the thermal shutdown feature, specifically on TSHUT. This post https://e2e.ti.com/support/processors/f/791/p/680839/2512053 says that the values are fixed and can't be accessed by software. However, the latest TRM says it can be accessed. Why was this control added, and are you able to write to it? The second question is on the values for this register. This post https://e2e.ti.com/support/processors/f/791/p/583110/2156914 says it's fixed to 123C for industrial/commercial grades devices. Is this true for all devices, even though they're only rated to less than 123C?
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Forum Post: Linux/AM3352: kernel is not seeing sdcard partitions
Part Number: AM3352 Tool/software: Linux We have beaglebone balck based custom board with 512MB RAM and 4GB eMMC and SdCard socket ( with 2GB SDcard) I used following script to partition SDcard DRIVE="/dev/sdc" umount "${DRIVE}"[0-9]* wipefs -a "${DRIVE}" #Erase all the partitions on the SDCard wipefs -a ${DRIVE}[0-9]* || true parted --script -a optimal ${DRIVE} \ mklabel msdos \ mkpart primary fat16 128KiB 32MiB \ toggle 1 boot \ mkpart primary ext4 32MiB 100% \ sync blockdev --flushbufs "${DRIVE}" mkfs.vfat -n BOOT /dev/sdc1 sync yes | mkfs.ext4 -j -L rootfs /dev/sdc2 sync I copied MLO, u-boot.img, uImage, test.dtb and when I try to boot from SDcard, Board boots till SPL, U-Boot, kernel BUT kernel is not able to see the RFS partition on SDcard. To debug the issue I booted board from NFS with same kernel and dtb. I see that fdisk -l on the board gives following result # fdisk -l Disk /dev/mmcblk0: 1983 MB, 2079326208 bytes, 4061184 sectors 63456 cylinders, 4 heads, 16 sectors/track Units: cylinders of 64 * 512 = 32768 bytes Device Boot StartCHS EndCHS StartLBA EndLBA Sectors Size Id Type /dev/mmcblk0p1 * 0,33,3 17,2,4 2048 67583 65536 32.0M c Win95 FAT32 (LBA) Partition 1 does not end on cylinder boundary /dev/mmcblk0p2 17,2,5 1023,30,60 67584 4061183 3993600 1950M 83 Linux Partition 2 does not end on cylinder boundary Found valid GPT with protective MBR; using GPT but I don't see any partitions being reported in /proc/partitions, look at output below, there are eMMC partitions being reported but kernel is not able to detect SDcard partitions. # cat /proc/partitions major minor #blocks name 1 0 16384 ram0 1 1 16384 ram1 1 2 16384 ram2 1 3 16384 ram3 1 4 16384 ram4 1 5 16384 ram5 1 6 16384 ram6 1 7 16384 ram7 1 8 16384 ram8 1 9 16384 ram9 1 10 16384 ram10 1 11 16384 ram11 1 12 16384 ram12 1 13 16384 ram13 1 14 16384 ram14 1 15 16384 ram15 179 0 2030592 mmcblk0 179 23 3735552 mmcblk1 179 24 127 mmcblk1p1 179 25 127 mmcblk1p2 179 26 128 mmcblk1p3 179 27 1024 mmcblk1p4 179 28 1024 mmcblk1p5 179 29 1024 mmcblk1p6 179 30 1024 mmcblk1p7 179 31 5120 mmcblk1p8 179 32 5120 mmcblk1p9 179 33 5120 mmcblk1p10 179 34 1024 mmcblk1p11 179 35 1024 mmcblk1p12 179 36 1024 mmcblk1p13 179 37 5120 mmcblk1p14 179 38 512000 mmcblk1p15 179 39 512000 mmcblk1p16 179 40 102400 mmcblk1p17 179 41 76800 mmcblk1p18 179 42 1048576 mmcblk1p19 179 43 400384 mmcblk1p20 179 44 54272 mmcblk1p21 179 45 999424 mmcblk1p22 179 69 2048 mmcblk1boot1 179 46 2048 mmcblk1boot0 Any suggestions pointers as to why kernel is not detecting SDcard partitions ? I am getting following prints on fdisk -l output but I am not sure what is wrong Partition 1 does not end on cylinder boundary Partition 2 does not end on cylinder boundary
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Forum Post: AM5728: Can NOT start when power on
Part Number: AM5728 Hi, I'm using TMDSEVM572X now. But sometimes the board can NOT start up when power on. Could you please tell me what's the reason? Thanks. Kevin Xiong
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Forum Post: Linux/TMDX654GPEVM: Out-of-the-box build all has errors
Part Number: TMDX654GPEVM Tool/software: Linux Installed Linux SDK and followed this: http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Overview_Getting_Started_Guide.html#top-level-makefile Build Everything out-of-the-box has the following errors: failed making /example-application/pru-icss-5.4.0/labs and “no rules to make target ‘sysfw-image’ I have not checked the script but does it have enough components built to install the Matrix example? Thanks.
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Forum Post: Linux/AM5728: UART baudrate 460800
Part Number: AM5728 Tool/software: Linux Hi, I've successed config UART1( dts statue=ok ) to work at 115200. Now I need 460800,I tried to use : cfsetispeed(&newtio, B460800) config the baudrate to 460800.But I got wrong data through UART.
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Forum Post: TMS320C6748: How can I confirm that the L1P cache is enable for the code?
Part Number: TMS320C6748 Hi! I am testing the read speed of nand flash using the DMA mode,I found when starting the DMA transfer and finishing the transfer,there are more code processing time before real transfer and after the transfer,I watch the OE(read) signal and using a GPIO to notice the start and finsh point of DMA transfer.so I guess maybe this is caused that the code is processing in the DDR(clock is 150M),so I want to let the code process in the L1P cache,I use the demo code of cache,but we don't know weather the cache is enable.the operation is below:(I don't use the RTOS) 1. CacheEnableMAR((unsigned int)0xc0000000 NAND_DATA_BUFF_SIZE/2); //set the DDR address to the cache /* Enable Cache */ CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_256K); Is it correct?how can I do to enabel the L1P cache for the code? Thanks a lot.
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Forum Post: Linux/AM5728: How to use Camera Module(0v1063) with old PSDK(v02.00.00.00)
Part Number: AM5728 Tool/software: Linux Hi, I want to use a camera module(0v1063) with GP EVM and the old PSDK(v02.00.00.00). I need to fix device tree file(am57xx-evm.dts), but how do I change it? The following changes did not work. I referred to the device tree (am57xx-evm-reva3-cam-ov10635.dts) included in PSDK (05.02.0.10). --- am57xx-evm.dts 2019-04-19 11:13:30.000000000 +0900 +++ am57xx-evm_psdkv2_cam-mod.dts 2019-04-19 11:14:12.000000000 +0900 @@ -7,6 +7,21 @@ interrupt-parent = ; model = "TI AM572x EVM"; + clk_ov10635_fixed { + phandle = ; + clock-frequency = ; + #clock-cells = ; + compatible = "fixed-clock"; + }; + + clk_ov10635 { + phandle = ; + enable-gpios = ; + clocks = ; + #clock-cells = ; + compatible = "gpio-gate-clock"; + }; + chosen { }; @@ -3899,26 +3914,23 @@ status = "okay"; clock-frequency = ; - mt9t11x@3C { - compatible = "aptina,mt9t111"; - reg = ; - reset-gpios = ; - oscen-gpios = ; - powerdown-gpios = ; - bufen-gpios = ; - camen-gpios = ; + ov10635@30 { + reset-gpios = ; + reg = ; + powerdown-gpios = ; + clocks = ; + clock-names = "xvclk"; + compatible = "ovti,ov10635"; port { endpoint { - remote-endpoint = ; - hsync-active = ; + phandle = ; vsync-active = ; - pclk-sample = ; - input-clock-freq = ; - pixel-clock-freq = ; + remote-endpoint = ; + pclk-sample = ; linux,phandle = ; - phandle = ; + hsync-active = ; }; }; }; dmesg is as follows. root @ am57xx-evm: ~ # dmesg | grep ov1063 [4.497251] of_get_named_gpiod_flags: can't parse 'mux-gpios' property of node '/ ocp / i2c @ 4807c000 / ov10635 @ 30 [0]' [4.528796] ov1063x 4-0030: Failed writing register 0x0103! [4.681908] ov1063x: probe of 4-0030 failed with error -121 (Please visit the site to view this file) (Please visit the site to view this file)
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Forum Post: RTOS/AM3352: which example can I use for study EDMA
Part Number: AM3352 Tool/software: TI-RTOS Dear sir: I want to test EDMA on AM335X, using RTOS, which example can I refer to reference ?
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Forum Post: Linux/DRA745: VSDK yocto filesystem optimizing
Part Number: DRA745 Tool/software: Linux Hi, experts, I use vsdk0304 linux and I want to use Yocto to optimize the filesystem. 1. could you provide the current version VSDK0304 config in Yocto? ( I only can get the environment of filesytem(PSDK). 2. Could you give me gudie to how to optimize the filesystem in Yocto? Best Regards, Widic
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Forum Post: RTOS: How to run TIDL OD usecase with imported model?
Tool/software: TI-RTOS Hi, I'm trying to run TIDL OD usecase with imported model. I used voc0712_ssdJacintoNetV2_iter_120000.caffemodel and voc0712\JDetNet\ssd768x320_ds_PSP_dsFac_32_hdDS8_0\test_quantize\deploy.prototxt. I converted caffe model by using this command `tidl_model_import.out.exe D:\TI_TDA2x\ti_dl\test\testvecs\config\import/tidl_import_JDetNet.txt` and could see converted result(Net.bin & Param.bin) I copied that files into SD card and executed TIDL OD usecase. However, the video stopped when i execute usecase. The attached image is that. And if i recopied prebuilt jedetNet.bin, jedetParam.bin, it works well. Is there any thing to edit when i use VOC Dataset? Thank you in advance. Regards Yoo.
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Forum Post: Linux/TMS320C6678: PCIE driver. and ap for TMS320C6678 with Linux CPU
Part Number: TMS320C6678 Tool/software: Linux Hi Experts, Where do I get PCIE driver. and ap for TMS320C6678 with Linux CPU? Derek
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Forum Post: 66AK2H06: EMIF16 access fails with DPLL 1.2GHz
Part Number: 66AK2H06 Hi, My customer is evaluating EVMK2H and connecting it with FPGA. FPGA is connected to EMIF16. When 66AK is running below 1.2GHz, there is no problem. But if DPLL is configured to 1.2GHz, FPGA write access is failed. They checked two EVMs and found one board works up to 1167.36MHz and other works up to 1044.48MHz. Customer thought it was too fast for EMIF/FPGA access then they changed EMIF parameters to slow down the access, but results were the same. Please see attached excel sheet for details. (Please visit the site to view this file) Even when DPLL is set to 1.2GHz, read accesses from FPGA work fine and DDR accesses(read and write) are also OK. What is the possible cause of the issue? Thanks and regards, Koichiro Tashiro
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Forum Post: RTOS/TMS320C6678: I2C Busy Bit
Part Number: TMS320C6678 Tool/software: TI-RTOS Dear, I have two I2C devices connected to C6678, Observed that I2C busy bit is set before starting the transaction itself. Observed that after removing I2C from out of reset, busy bit is set. We are configuring the I2C controller in the following way, /* Set I2C in reset */ I2CR->ICMDR &= (~CSL_I2C_ICMDR_IRS_MASK); RCI_delaycycles(100); /* Set Own Address */ I2CR->ICOAR = I2C_OWN_ADDR; /* * Set Default I2C High and Low Clock Hold */ I2CR->ICPSC = I2C_PRESCALER; I2CR->ICCLKL = I2C_CLK_LOW; I2CR->ICCLKH = I2C_CLK_HIGH; /* * Enable the Xmt, Master Mode */ I2CR->ICMDR = ( CSL_I2C_ICMDR_MST_MASK | CSL_I2C_ICMDR_TRX_MASK | CSL_I2C_ICMDR_FREE_MASK ); /* * Take I2C Out of Reset */ I2CR->ICMDR |= CSL_I2C_ICMDR_IRS_MASK; RCI_delaycycles(100); Could you please share me the reasons for the busy bit to be set. NOTE: We removed both devices from the I2C chain, Thanks you, Mounika
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Forum Post: AM3352: Video feasibility study 1080p 24bpp 30fps
Part Number: AM3352 Hello Champions, I need to double check with you if AM3352 is be able to manage a Full HD 1080p 24bpp @ 30fps . Don't need any graph acceleration, need "only" to play Video on a 10inch display. Standing to DS , AM3352 can manage up to 2048x2048 24bpp @ 30fps ( 126Mhz pixel clock: if I well understood LCD_DATA is sampled only on one edge of LCD_PCLK ) -> Memory bandwidth should be 360MB/s compatible with any DDRx supported . In my case : 1080x1920 x 24bpp x 30fps I should need a 62Mhz pixel clock and 188MB/s memory bandwidth , well covered my AM3352 's specs . Are my computation right ? can I play a Full HD 30fps Video with Sitara AM3352 ? There's a correlation between AM3352 clock and the Video capabilities , rephrasing , What is the suggested AM3352 clock speed to manage the Video defined above ? Thank you, Paolo
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Forum Post: CCS/66AK2G12: SPI register access issue in PRU
Part Number: 66AK2G12 Tool/software: Code Composer Studio I use K2GEVM to do some interface verification.I want to use the PRU to access some SPI device. I found the SPI register read is OK, I could get the SPIREV content by constant table or global address(base addr:0x21805400/0x21805C00). But the SPI register write operation is not OK.(checked this by read back SPI register and see register contents in ARM site). I can write the SPI register in ARM, so the SPI hardware should be OK. this is the config in my PRU CCS project: SPI0 : org = 0x21805400 len = 0x00000200 CREGISTER=6 volatile __far pruSpi CT_SPI0 __attribute__((cregister("SPI0", far), peripheral)); Could you provide me some demo code in C how the PRU operate the SPI register? BTW, I found there is only 2 SPI interface in the constant table, if I want to use 3 or 4 SPI in PRU, what should I do by using constant table? The access by global address may be a little slow for me.
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