Hello Jonas, The PRU-ICSS has two methods of keeping track of time: The Industrial Ethernet Peripheral timer (sometimes called IEP timer, sometimes called Industrial Ethernet Timer in the AM335x technical reference manual or TRM), and the cycle count register. The IEP timer is probably what you are looking for. Regards, Nick
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Forum Post: RE: Linux/AM3354: Access to clocks/timers in PRU assembly programs
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Forum Post: RE: Linux/AM3354: Access to clocks/timers in PRU assembly programs
We do not have an assembly example of using the IEP timer, but we have a C example within the PRU Software support package (in your Linux Processor SDK under example-applications/pru-icss-x.x.x/examples/am335x/PRU_IEP, or at the git repo git.ti.com/.../ ). General TI PRU resources are at processors.wiki.ti.com/.../PRU-ICSS Regards, Nick
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Forum Post: AM5728: pinmux project for the beaglebone-x15 or the IDK AM5728
Part Number: AM5728 Is it possible to get the pinmux project for the beaglebone-x15 or the IDK AM5728
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Forum Post: Linux/66AK2E05: Gcc atomic operation support on ARM A15 cores
Part Number: 66AK2E05 Tool/software: Linux Hi, I am building a small library for atomic operations support using GCC built-in "__sync" operations, for example for 32bit values: void atomic_set_u32(uint32_t *ptr, uint32_t value) { __sync_synchronize(); *ptr = value; __sync_synchronize(); } uint32_t atomic_get_u32(uint32_t *ptr) { __sync_synchronize(); return *ptr; } This seems to be working on x86 and I would like to know if GCC __sync operations are supported on ARM15 cores for linux application ? Can I find more information on atomicity support for Linux on Keystone ARM15 cores? Thank you
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Forum Post: DRA76P: Missing mass information of DRA76P
Part Number: DRA76P A customer is asking for weight information of the DRA76P . When looking at the material/content information of DRA767P, I found following data where mass of the device is still shown as 0.0mg. Where can I find valid mass data for this device? Best regards, Manfred
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Forum Post: Linux/TMDX654GPEVM: Remote matrix demo
Part Number: TMDX654GPEVM Tool/software: Linux I am following the Matrix User's Guide: http://software-dl.ti.com/processor-sdk-linux/esd/docs/05_02_00_10/linux/Examples_and_Demos_Matrix_User_Guide.html I power up the EVM with the out-of-the-box SD Card without the display module connected. I want to use the remote matrix option instead. The ipconfig command is not found so I use "ip address": root@am65xx-evm:~# ip address 1: lo: mtu 65536 qdisc noqueue state UNKNOWN group default qlen 1000 link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 inet 127.0.0.1/8 scope host lo valid_lft forever preferred_lft forever inet6 ::1/128 scope host valid_lft forever preferred_lft forever 2: eth0: mtu 1500 qdisc mq state UP group default qlen 1000 link/ether f4:84:4c:ed:38:8d brd ff:ff:ff:ff:ff:ff inet6 fe80::f684:4cff:feed:388d/64 scope link valid_lft forever preferred_lft forever 3: eth1: mtu 1500 qdisc fq_codel state DOWN group default qlen 1000 link/ether 8e:10:86:74:8b:a3 brd ff:ff:ff:ff:ff:ff 4: eth2: mtu 1500 qdisc fq_codel state DOWN group default qlen 1000 link/ether fa:67:b5:40:c6:bc brd ff:ff:ff:ff:ff:ff eth0 does not have an IPV4 address. So I tried to connect Ethernet cable and enter inet6: http://[fe80::f684:4cff:feed:388d]:80 to the address bar. The browser prompted: This page isn't working. [fe80::f684:4cff:feed:388d] did not send any data. ERR_EMPTY_RESPONSE. How do I get the out-of-the-box SD Card boot to work with the URL using Remote Matrix? Thanks.
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Forum Post: Linux/AM3352: is it possible to bring sdcard as mmc1 interface in Linux
Part Number: AM3352 Tool/software: Linux We are using Beaglebone black based custom board with 512MB RAM, 4GB eMMC and socket for SDcard, We have different mode we bringup board using SDcard and flash software on eMMC. When we boot board from SDcard it is detected as mmcblk0 and eMMC is detected mmcblk1. We want emmc to be on the mmcblk0 and SDcard on mmcblk1 reason being we have common scripts ( for boards which doesn't have SDcard those scripts refers eMMC as mmcblk1 ). So my question is it possible to make sdcard interface reported as mmcblk1 ?
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Forum Post: Compiler/TDA3: TDA3xx Example Csl_McSPI_MasterSlave_App McSPI Usage
Part Number: TDA3 Tool/software: TI C/C++ Compiler Hi. I want to run SPI communication example using TDA3xx-EVM board and TDA3xx custom board. To do this, I tried to use the csl_mcspi_masterslave_app example. But I do not know how to use it. Build without modifying the example and run it on the TDA3xx-EVM board and the TDA3xx custom board. As a result, both McSPI2 RX Timed out !! I printed a message. And I entered the while loop. Can I use this example without modifying the code? Or do I have to make the appropriate modifications? If so, please let me know what you need to do. I tried a little more. I connected SPI1 of TDA3xx custom board to SPI2 of TDA3xx-EVM. EVM Custom SPI2-D1 : 17 SPI1-D0 SPI2-CS0 : 20 SPI1-CS0 SPI2-SCLK : 22 SPI1-SCLK SPI2-D0 : 18 SPI1-D1 GND : 4 GND And PadConfig_prcmEnable has been modified. EVM HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_UART1_RXD, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_UART1_TXD, 0x00000000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_CSO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_SCLK, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_DO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_D1, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_CSO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_SCLK, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_DO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_D1, 0x00040000); Custom Board HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_CSO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_SCLK, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_DO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_D1, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_UART2_RXD, 0x00060000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_UART2_TXD, 0x00060000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_UART2_CTSN, 0x00070000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_UART2_RTSN, 0x00060000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_CSO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_SCLK, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_DO, 0x00040000); HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI2_D1, 0x00040000); And at the beginning of the main () function code of the custom board, "uartBaseAddr = SOC_UART2_BASE;" Added. The Custom Board is UART2 communication with UART. Is this setting correct? And I know that TDA3xx-EVM can set MISO, MOSI of D0 or D1, do not need to modify? If I need to fix it, please let me know how. After rebuilding, I will tell you the result. Thank you.
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Forum Post: RE: RTOS/AM3359: UIA v2.21.02.07 can not download
Hi, That link should be working. We are looking into it. I've attached it below in case you need it now (and I'm pleasantly surprised that it allowed me to attach such a large file). (Please visit the site to view this file) Todd
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Forum Post: RE: Linux/AM5718: Multiple PTP instances on dual interfaces of PRU ETH
Paritosh, Try something like this for your cfg: [global] sanity_freq_limit 0 step_threshold 0.000002 tx_timestamp_timeout 10 logMinPdelayReqInterval 0 logMinDelayReqInterval 0 logSyncInterval 0 logAnnounceInterval 0 priority2 128 twoStepFlag 1 summary_interval 0 fault_reset_interval 1 [eth2] boundary_clock_jbod 1 egressLatency 726 ingressLatency 186 delay_mechanism P2P network_transport L2 fault_reset_interval 0 [eth3] boundary_clock_jbod 1 egressLatency 726 ingressLatency 186 delay_mechanism P2P network_transport L2 fault_reset_interval 0 Please send the updated console output. Thanks, Brad
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Forum Post: RE: Mobile Application Processors: DVFS and ABB supported?
Thanks for your help. I have read the technical reference manual for OMAP3+ processors. Both of DVFS and ABB are supported now, however, I cannot get the following information: 1) whether we can use both techniques simultaneously; 2) whether this phenomenon is existed that one technique uses a slow time-scale to adjust the voltage/frequency, while the other technique uses a fast time-scale.
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Forum Post: RE: DRA76P: Missing mass information of DRA76P
Manfred, It is approximately 2.4g. Regards, Kyle
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Forum Post: RE: TMS320C5535: SPI peripheral more than doubles current consumption
Mark, The schematics I sent you represents how the C5535 is currently wired. I have not removed any of the 0ohm resistors yet. This product is still going through its prototype/development phase so the 0ohm resistors are there in case any changes or jumper modifications needs to be made. I have not had any major problems with the C5535 besides this weird SPI power issue. I will consider asking for the C5535 eZDSP if resolving this issue takes longer than expected. I did as you suggested and changed the PPMODE from MODE 1 to MODE 6. Unfortunately the same issue persists. The current does scale somewhat with different PLL speeds: 100MHz: ~22mA without SPI initialized, ~70mA with SPI initialized 60MHz: ~13mA without SPI initialized, ~60mA with SPI initialized However, changing the SPI CLK speed did not make any noticeable difference in current consumption: /* Set the hardware configuration */ spiCfg_ADS.spiClkDiv = 20; spiCfg_ADS.wLen = SPI_WORD_LENGTH_32; spiCfg_ADS.frLen = 1; spiCfg_ADS.wcEnable = SPI_WORD_IRQ_DISABLE; spiCfg_ADS.fcEnable = SPI_FRAME_IRQ_DISABLE; spiCfg_ADS.csNum = SPI_CS_NUM_0; spiCfg_ADS.dataDelay = SPI_DATA_DLY_0; spiCfg_ADS.csPol = SPI_CSP_ACTIVE_LOW; spiCfg_ADS.clkPol = SPI_CLKP_LOW_AT_IDLE; // SPI MODE 1 spiCfg_ADS.clkPh = SPI_CLK_PH_RISE_EDGE; 100MHz / 20 = SPI clock of 5MHz 100MHz / 1000 = SPI clock of 100kHz In both cases, the current consumption was still at ~70mA after SPI_config() was called. Best, Eddie
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Forum Post: RE: Linux/AM4378: u-boot not running DHCP, ethernet in half duplex mode
well part of my problem with doing it in linux is this: we have the ethernet PHY reset on a gpio line. in u-boot in board.c i take the PHY out of reset. when linux loads it appears to put the PHy back into reset. i only know this because 1) the PHY LED is off when the kernel loads and 2)the kernel can't find the PHY but u-boot can. i thought that if i took it out of reset in u-boot that the kernel wouldn't touch it but apparently it does. what can i do about this?
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Forum Post: RE: RTOS/AM3359: Missing platform package 'ti.platforms.evmAM3359'
Attempts to create the example projects in PRU-ICSS-HSR-PRP-DAN_01.00.04.02 using AM335x PRSDK v4.3 fail. Per the comments in the projectCreate.bat file distributed with PRU-ICSS-HSR-PRP-DAN_01.00.04.02: ::File_Name : projectCreate.bat ::Description : This batch file can create CCS projects based on the project settings specified in the project create options files. ::Date : 19-Oct-2016 ::File_Version : 2.0.1 - Created initial version for generating PRU-ICSS-HSR-PRP-DAN package example projects. :: : 2.0.2 - Added PROCESSOR Argument support ::Usage Syntax: :: projectCreate.bat [SOC] [PROCESSOR] [PROJECT_NAME] :: :: [SOC] Valid values are AM572x, AM571x, AM57xx, AM335x, AM437x, K2G, AMIC11x :: [PROCESSOR] Valid values are arm :: [PROJECT_NAME] Valid values are hsr_app, prp_app, hsr_lib, prp_lib, timeSync_lib, snmp_core_stack :: ::Usage example 1: :: projectCreate.bat AM572x arm hsr_app :: -Creates hsr_app application project for AM572x ARM core :: ::Usage example 2: :: projectCreate.bat AM57xx arm snmp_core_stack :: -Creates snmp_core_stack library project which can be used for both AM571x and AM572x platforms ARM core :: Yet this fails in practice: This follows a fresh install of both the PRU-ICSS-HSR-PRP-DAN_01.00.04.02 and AM335x PRSDK v4.3 packages with no modifications made to the projectCreate.bat file. Please provide instructions on how to create the example projects for the AM335x from the PRU-ICSS-HSR-PRP-DAN_01.00.04.02 package?
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Forum Post: RE: RTOS/AM3359: Missing platform package 'ti.platforms.evmAM3359'
The image I tried to insert in my previous message was dropped. The image below shows the projectCreate batch file failure
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Forum Post: RE: 66AK2H12: Cache coherency seems not working
Hi , Could you please follow this ?
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Forum Post: RE: Linux/AM5708: Qt 5.12 Web engine High CPU usage
Hi Vivek, Not from the perspective of the web engine, but at the physical level. Just want to let you know how to check the GPU power and frequency state. But your comments on the qt opengl examples not using that much CPU seem to confirm it as well. Regards, Ahmad
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Forum Post: RE: RTOS/AM3352: Reading USB DevCtl crashes system
Eric, For #1, using the non-CDC program: I'm not sure what you mean by "Can you confirm that without MMU" but at the entry point to main(), 0x47400000 and 0x47401460 both show up as ???????? in the memory browser. The MMU table is at 0x80458000. The first thing in main is a call to a function MMUInit(). After returning from that function, 0x47400000 and 0x47401460 are still unchanged, unreadable. If I then let the program continue on and break at the point where the code is going to read from 0x47401460, both 0x47400000 and 0x47401460 (and everything in between) are now readable in the memory browser. Rechecking the MMU table at that point does not show any changes. For #2, using the CDC program: At the entry point to main(), 0x47400000 and 0x47401460 both show up as ???????? in the memory browser. The MMU table is at 0x80870000. I entered 0x47400E12 at address 0x80870010 (not sure if the exact location in the table mattered so I put it near the beginning) . After that change, reading from 0x47400000 and 0x47401460 is still unchanged, unreadable. Again, the first thing in main is a call to a function MMuInit(). After returning from that function, 0x47400000 and 0x47401460 are still unchanged, unreadable. The MMU table is still intact, I still have 0x47400E12 at address 0x80870010 there do not appear to be any other changes. If I then let the program continue on and break at the point where the code is going to attempt to read from 0x47401460, MMU table still appears unchanged, 0x47400000 and 0x47401460 are still unchanged, unreadable. The MmuInit function is the same in both programs, shown below. It would appear that there must be a call to something in the non-CDC USB device driver that changes whether the MMU blocks 0x47400000 or not but it does so in a way that doesn't affect what appears to be a static MMU table. Kevin Jennings ===== Start of MmuInit ===== static void MmuInit(void) { unsigned int index; for (index = 0; index = 0x800 && index < 0x840) || // DDR (index == 0x403) || // OCMC (index == 0x402)) // SRAM { pageTable[index] = (index << 20) | CACHEABLE_TLB_ATTR; } /* Set the non-cacheable memory attributes */ else { pageTable[index] = (index << 20) | NORM_TLB_ATTR; } } /* Invalidate the TLB entries */ CP15TlbInvalidate(); CP15DomainAccessClientSet(); /* Set TTB0 value. We use only TTB0 here (N = 0) */ CP15Ttb0Set(((unsigned int )pageTable) | RGN_L2_WBWA); /* Enables MMU */ CP15MMUEnable(); /* Enable Data Cache */ CP15DCacheEnable(); /* Disable Instruction Cache*/ CP15ICacheEnable(); } ===== End of MmuInit =====
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Forum Post: RE: AM5728: pinmux project for the beaglebone-x15 or the IDK AM5728
Please see this post by Ahmad: e2e.ti.com/.../2422239
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