Hi, Do you use RTOS or baremetal? If RTOS, there would be something like below in the configuration: Mmu.enableMMU = true; // Force peripheral section to be NON cacheable strongly-ordered memory var peripheralAttrs = { type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor tex: 0, bufferable : false, // bufferable cacheable : false, // cacheable shareable : false, // shareable noexecute : true, // not executable }; // Define the base address of the 1 Meg page // the peripheral resides in. var peripheralBaseAddr = 0x44e00400; // Configure the corresponding MMU page descriptor accordingly Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs); // Define the base address of the 1 Meg page // the peripheral resides in. var peripheralBaseAddr = 0x481a6000; // UART3 and other // Configure the corresponding MMU page descriptor accordingly Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs); var peripheralBaseAddr = 0x47400000; // USBSS // Configure the corresponding MMU page descriptor accordingly Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs); Regards, Eric
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Forum Post: RE: RTOS/AM3352: Reading USB DevCtl crashes system
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Forum Post: RE: RTOS/AM3352: Reading USB DevCtl crashes system
Hi, If you using bare metal and code is similar to pdk_am335x_1_0_xx\packages\ti\starterware\, there is an API call: MMUConfigAndEnable(). It is implemented inside pdk_am335x_1_0_xx\packages\ti\starterware\examples\example_utils. There is a call MMUMemRegionMap(®ionDev, (uint32_t*)pageTable); you need to look at what regions are covered. Regards, Eric
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Forum Post: RE: Linux/AM4378: linux fails to boot
tada fyi the dts file is a work in progress. we are still trying to get stuff up and running on this board (Please visit the site to view this file)
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Forum Post: AM3358: Routing with two EPHYs
Part Number: AM3358 I am trying to use two RGMII Ethernet ports on the AM3358ZCZA100. From what I can tell, it only has one MDIO/clk and Data port. Do I route that one port to both my PHY’s? I am using the TI DP83867IRRGZT for the PHY. Thanks, Brian
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Forum Post: TMDSDSK6416: Generate short pulse with DSP Timer
Part Number: TMDSDSK6416 Hello, I'm trying generate short pulses with DSP's 32-bit timer. I'm using the DSK6416 board. I need to have pulse widths as short as 50ns-100ns and be able to change the duty-cycle. I try to read the CNT register of the timer and set DATOUT to be driven on TOUT pin of timer when the proper width has reached. The problem is that when I use the TIMER_setDatOut API it is not possible to get 50-100ns pulse widths. The shortest pulse width you can get is 150ns. Here is my simple code: #include #include #include TIMER_Handle hTimer; TIMER_Config MyConfig = { 0x00000300, //Clock mode, Internal clock source f_cpu/8, DATOUT is driven on TOUT DSK runs at 1GHz 0x0000007D, //f=125MHz/(this value) 1MHz frequency as an example 0x00000000 }; void main() { CSL_init(); TIMER_config(hTimer,&MyConfig); hTimer = TIMER_open(TIMER_DEV0,0); TIMER_start(hTimer); while(1) { if(TIMER_getCount(hTimer)<10){ TIMER_setDatOut(hTimer,1);} else { TIMER_setDatOut(hTimer,0);} } } . Thank you for your help
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Forum Post: Linux/BEAGLEBK: Beaglebone Black changing PHY from 100M to Gigabit
Part Number: BEAGLEBK Tool/software: Linux Hi, We are thinking to change our design that bases on Beaglebone Black from a 100M PHY to a Gigabit PHY. The questions are: 1. What software changes will require at u-boot, device tree, and Linux kernel levels? 2. Will this cause any performance issues for software? Thank you!
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Forum Post: RTOS/TDA2EXEVM: vision sdk 3.04 compile error
Part Number: TDA2EXEVM Tool/software: TI-RTOS Hi Previously vision sdk 3.03 works perfectly. Fresh download and install Vision SDK 3.04, windows environment. Compile error as photo Please help. regards Chee Peng
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Forum Post: AM3352: BUG: soft lockup - CPU#0 stuck for 22s! [kdetect:18241]" ?
Part Number: AM3352 Hi, all i have a soft lockup problem in my custom board with PSDK v05.02 (linux kernel is v4.14.79). soft lockup come out some hours later after bootup. it will output every 22s, as below: [ 4588.017023] watchdog: BUG: soft lockup - CPU#0 stuck for 22s! [kdetect:18241] [ 4588.024234] Modules linked in: option ch34x(O) cdc_acm zl380tw(O) [ 4588.030400] CPU: 0 PID: 18241 Comm: kdetect Tainted: G O 4.14.79 #94 [ 4588.037918] Hardware name: Generic AM33XX (Flattened Device Tree) [ 4588.044043] task: d9c08c00 task.stack: d9cec000 [ 4588.048602] PC is at 0xb6f91820 [ 4588.051758] LR is at 0xb6f9179c [ 4588.054915] pc : [ ] lr : [ ] psr: 200f0010 [ 4588.061210] sp : bebceb00 ip : b698ca34 fp : bebceb5c [ 4588.066458] r10: bebceb58 r9 : 00000000 r8 : 00000000 [ 4588.071710] r7 : 00000373 r6 : b685217c r5 : b6858ec2 r4 : b6fabfe0 [ 4588.078269] r3 : 00000001 r2 : 00000000 r1 : b685217c r0 : b6858ec2 [ 4588.084832] Flags: nzCv IRQs on FIQs on Mode USER_32 ISA ARM Segment user [ 4588.092087] Control: 10c5387d Table: 99dc0019 DAC: 00000055 [ 4588.097864] CPU: 0 PID: 18241 Comm: kdetect Tainted: G O 4.14.79 #94 [ 4588.105379] Hardware name: Generic AM33XX (Flattened Device Tree) [ 4588.111499] Backtrace: [ 4588.114009] [ ] (dump_backtrace) from [ ] (show_stack+0x18/0x1c) [ 4588.121622] r7:00000000 r6:d9cec000 r5:c2f1e720 r4:c2f031a8 [ 4588.127334] [ ] (show_stack) from [ ] (dump_stack+0x24/0x28) [ 4588.134598] [ ] (dump_stack) from [ ] (show_regs+0x14/0x18) [ 4588.141788] [ ] (show_regs) from [ ] (watchdog_timer_fn+0x19c/0x1d0) [ 4588.149769] [ ] (watchdog_timer_fn) from [ ] (__hrtimer_run_queues.constprop.5+0x150/0x1e0) [ 4588.159736] r10:c2f1cb4c r9:c01b7070 r8:00000000 r7:c2f1cb40 r6:d9cec000 r5:c2f1e738 [ 4588.167601] r4:c2f1cb00 [ 4588.170156] [ ] (__hrtimer_run_queues.constprop.5) from [ ] (hrtimer_interrupt+0xa4/0x22c) [ 4588.180035] r10:c2f1cbb8 r9:c2f1cb00 r8:ffffffff r7:7fffffff r6:00000003 r5:d9cec000 [ 4588.187901] r4:c2f1cb00 [ 4588.190472] [ ] (hrtimer_interrupt) from [ ] (omap2_gp_timer_interrupt+0x30/0x38) [ 4588.199568] r10:c2f4e783 r9:dc006200 r8:00000010 r7:d9cedf14 r6:00000000 r5:dc006200 [ 4588.207432] r4:c2f0e140 [ 4588.209990] [ ] (omap2_gp_timer_interrupt) from [ ] (__handle_irq_event_percpu+0xb4/0x144) [ 4588.219868] [ ] (__handle_irq_event_percpu) from [ ] (handle_irq_event_percpu+0x24/0x60) [ 4588.229572] r10:bebceb58 r9:00000000 r8:dc008000 r7:00000001 r6:00000000 r5:dc006200 [ 4588.237437] r4:dc006200 [ 4588.239989] [ ] (handle_irq_event_percpu) from [ ] (handle_irq_event+0x64/0x90) [ 4588.248902] r5:00000000 r4:dc006200 [ 4588.252507] [ ] (handle_irq_event) from [ ] (handle_level_irq+0xb4/0x154) [ 4588.260896] r5:00000000 r4:dc006200 [ 4588.264513] [ ] (handle_level_irq) from [ ] (generic_handle_irq+0x2c/0x3c) [ 4588.272990] r5:00000000 r4:c2f4daf0 [ 4588.276590] [ ] (generic_handle_irq) from [ ] (__handle_domain_irq+0x5c/0xb0) [ 4588.285335] [ ] (__handle_domain_irq) from [ ] (omap_intc_handle_irq+0x3c/0x98) [ 4588.294254] r9:00000000 r8:10c53c7d r7:10c5387d r6:ffffffff r5:200f0010 r4:c2f83c88 [ 4588.302040] [ ] (omap_intc_handle_irq) from [ ] (__irq_usr+0x54/0x80) [ 4588.310083] Exception stack(0xd9cedfb0 to 0xd9cedff8) [ 4588.315165] dfa0: b6858ec2 b685217c 00000000 00000001 [ 4588.323389] dfc0: b6fabfe0 b6858ec2 b685217c 00000373 00000000 00000000 bebceb58 bebceb5c [ 4588.331608] dfe0: b698ca34 bebceb00 b6f9179c b6f91820 200f0010 ffffffff [ 4588.338254] r5:200f0010 r4:b6f91820 The detail log.txt and kernel config are attached. Thank you in advance.
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Forum Post: RE: RTOS/AM3352: Reading USB DevCtl crashes system
Kevin, >>>>>>>For the working (non-CDC driver) program, the only non-zero numbers are 40201E0E, 40301E0E, 48000E12, 48200E12, 80001E0E,...80601E0E. >>>>>>> Can you confirm that without MMU you can read 0x4740_0000 address in CCS or code? In the failure case, >>>>The non-working (with CDC driver) program had the exact same numbers, but also three more: 80701E0E, 80801E0E and 80901E0E which immediately followed 80001E0E,...80601E0E>>>>>>>>> Are you able to find out how those entries are added by your code? Then add a similar entry for 0x4740_0000 region? Regards, Eric
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Forum Post: RE: Linux/AM5718: For loop taking much time
Thanks, I want to know that my board have does not issue with hardware. so i just asking for doing same test on any AM5718 eval board because right now we does not have eval board. Thanks & Best Regards, Nikunj Patel
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Forum Post: RE: TMS320C6654: Clock LVDS Levels
On the rise and fall time: IDT datasheet says 300 ps for 20% to 80% so minimum Vpp differential swing is is 494 mV and that gives a slew rate of 0.988 mv/ps. So for the 250 mV mentioned in the datasheet the rise time comes to around 253 mV. Which is within the 50-350 mentioned in the datasheet. Did I get it right?
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Forum Post: RE: TMS320C6654: Clock LVDS Levels
Typo. Meant 253 ps as the rise time.
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Forum Post: RE: AM3354: Is it possible to keep USBx_DRVVBUS high?
Hi, No, there is no way to *keep* DRVVBUS when VBUS dropped. When VBUS drops below VBUSVALID, the MUSB controller turns off DRVVBUS and generates VBUSERROR interrupt. This is a hardware behavior and no software control on it. The only thing software can do is to try to re-start the host session again when handling the VBUSERROR interrupt. As stated in the TRM, the MUSB controller senses VBUS twice when entering host mode. USB_CTRL[OTGVDET_EN] is to enable/disable the first VBUS sensing. Clearing the bit can be used in the host-only design in which VBUS is not controlled by DRVVBUS but directly hooked to 5V power rail. This OTGVDET_EN bit doesn't affect DRVVBUS behavior.
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Forum Post: RE: Linux/AM5728: OpenCV API List and Performance Optimized for DSP
Hi, TI didn't optimize the API for DSP, but adding OpenCL to offload the algorithm computations to DSP. The algorithms are still from upstream source code. Please read the note under the performance comparison table. I don't know how you drew the conclusion of "In most cases, API with DSP is slower than ARM". In the performance comparison table, it shows the DSP is faster in 4 out of 7 example cases on AM57x, and 7 out of 7 on 66AK2H. Am I missing something? Having some computations offloaded to DSP, not only it gets better performance, but also offloading ARM core for some other tasks. Rex
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Forum Post: RE: PROCESSOR-SDK-DRA7X: Does TI has any userspace tool for userspace governer
Thanks for feedback What I am looking for is as below. 1. TI defines a set of OPP supported for a SOC. 2. TI defines a set of POH for a SOC based on OPP used either constant or a ratio of different OPP's 3. TI SDK provides option of freq scaling Now, to use frequency scaling, I want to understand if the available governors (ondemand or conservative) can ensure ratio of OPP to meet the POH criteria or can they be fine tuned OR is there any opensource application that uses userspace governor that can be fine tuned to meet ratio of OPP to in turn meet the POH.
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Forum Post: RE: Linux/AM5728: Any impact on Linux due to the chosen 32MB CMEM location in RAM?
Paritosh, [quote user="Paritosh Dixit"]- Is there any (performance or functionality) impact on Linux, if we use a continuous 32MB CMEM allocation somewhere in the middle of RAM[/quote] I don't think so. The Linux RAM quickly becomes fragmented whether you have one "chunk" or two, so I wouldn't expect this to matter. Also, FYI, this location was chosen such that even if you had a small amount of memory you wouldn't need to relocate CMEM. [quote user="Paritosh Dixit"] Another related question is: We are not using ipu2. How can we free up resources used by ipu2 ? Simply by below DTS change? ipu2_cma_pool: ipu2_cma@95800000 { status = "disabled"; }; [/quote] You can check if you have correctly disabled the IPU2 pool with this command: root@am57xx-evm:~# dmesg | grep -i cma [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB [ 0.000000] Reserved memory: initialized node ipu2_cma@95800000 , compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB [ 0.000000] Reserved memory: initialized node dsp1_cma@99000000 , compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB [ 0.000000] Reserved memory: initialized node ipu1_cma@9d000000 , compatible id shared-dma-pool [ 0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB [ 0.000000] Reserved memory: initialized node dsp2_cma@9f000000 , compatible id shared-dma-pool [ 0.000000] cma: Reserved 24 MiB at 0x00000000fe400000 I'm not sure if disabling it is sufficient or if you need to use /delete-node/.
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Forum Post: RE: Linux/AM5728: Some problems when I m designing mechanisms of synchronization between A15/C66/M4
Hi, That means the C66x CPU ISR can't handle the interrupt so quickly. It is a bit strange. What is inside your ISR code? Is it very simple or you have an estimate how many cycles it take to run the ISR? Do you use SYSBIOS to register the interrupt? In the C66x ISR may be you just add a counter and a timestamp (TSCL) and remove other codes, you can record the time stamp each time the ISR is entered and do a timestamp difference, you should expect the delta match your clock frequency. Does it the number make sense? Also how fast you run the DSP? 600 MHz or 750 MHz? Regards, Eric
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Forum Post: RE: Linux/AM5728: Any impact on Linux due to the chosen 32MB CMEM location in RAM?
Hi, There won't be any performance or functionality impact when changing CMEM location or size. Yes. The cma will not be allocated when the status is set to disabled. Rex
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Forum Post: RE: Linux/AM6548: AM6548 PRU, RGMII with 100 MBit for DP83TC811 PHY won't work
Hello Bjoern, Please attach your boot log and dts file. Regards, Nick
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Forum Post: RE: Linux/LINUXSDK-OMAPL138: Dynamic Voltage and Frequency Scaling (DVFS) on OmapL138 Running Linux Kernel 3.10.12 Affecting USB and Ethernet
[quote user="Shyam G"] Frequency (Mhz) Current Measured(mA) 300 (290-320)mA 200 (275-290)mA 100 (255-270)mA [/quote] Based on the OMAP-L138 power spreadsheet, if I start with a typical 300 MHz application, I see: 300 MHz (1.2V) -> 479 mW 200 MHz (1.1V) -> 323 mW 100 MHz (1.0V) -> 205 mW So I reduced power by 156 mW when going from 300 to 200 MHz. I then reduced power another 118 mW when going to 100 MHz. Given that your numbers are of a 5V source, the corresponding power reductions were 30mA x 5V = 150mW when transitioning from 300 MHz to 200 MHz. Similarly your power reduction was 20mA x 5V = 100mW when transitioning from 200 MHz to 100 MHz. From what I can see, your power reduction is in line with our power spreadsheet. I recommend that you verify the CVDD rail is correctly changing voltages to corresponding with the operating points. If it's not changing you would not get the full power reduction. If you'd like to reduce your power consumption, please revisit the peripherals that are enabled by PSC. I can see in your gel dumps that literally every peripheral in the device is enabled with the exception of SATA. Best regards, Brad
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