Forum Post: RE: Real-time streaming switching based on DM8168 decoding
Linux mem=1002M is not a supported configuration in DVR RDK. Did you make the memory map change or did the third party make the change ?Pls share the map file.Also are you sure your board is populated...
View ArticleForum Post: RE: C66x sRIO Discovery Timer and Silence Timer Configurations
Sorry we need to clean the docs up a bit here, there are legacy references to srv_clk that need to be replaced. My current understanding is below, but I’m still waiting on confirmation from design....
View ArticleForum Post: AIS CRC calculation and operation (C6748)
A continuation of this threadhttp://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/t/119062.aspxbut for the C6748.I am writing a user bootloader that will use the AISGEN format for the...
View ArticleForum Post: RE: AIS CRC calculation and operation
Well...it been two years and the TRMs are still wrong. This thread has been been very helpful with my attempts to do the same with the C6748. Thanks for that. Not so happy that the C6748 CRC is not...
View ArticleForum Post: RE: DM365 intermittent hang when configuring AEMIF
HiDid you solve the halt problem ? I meet the same problem with you. But if you change adap_emac->TXTEARDOWN = 0; -> adap_emac->TXTEARDOWN = 1, the halt problem disappeared, though the correct...
View ArticleForum Post: Some questions about the C6678 SmartReflex voltage
First,in the Hardware Design,the description is "The intended range of operation is between 31 and 50 (0.905 V – 1.020 V), operation outside this range may impact device reliability or performance."But...
View ArticleForum Post: RE: C5535: VSSRTC pin handling
Hi Steve,Thank you for response/According to customer experiment, if they connected the VSSRTC to the board ground with using external crystal, the application which used C5535 showed an improved...
View ArticleForum Post: RE: DM8168 report Exception
Badri, thanks for your reply!I have done DDR byte wise s/w leveling, but not resolve the problem. Now reduceing DDR frequency to 531MHz, It work stability.
View ArticleForum Post: RE: DM8168 VOUT1 output discrete sync YUV422 16bit data
Brijesh,No, It can output high and low.but not sync to other signal.So the horizontal resolution is not right,always less than 1920.I set pinmux as the below. In vps_platformTI816x.c file, static Int32...
View ArticleForum Post: RE: DVR-RDK 3.5 encode jpeg
Hi Badri, Thanks very much for your suggestion, I will have a try on it. Zhihui
View ArticleForum Post: RE: NSF LINK leads to dropping frame
Hi Badri, Thanks for your reply!I have modified my usecase as this:(video capture, OSD, Swms and Display) --> Merge2-->Select3--+-->NSF0-+-->Merge4 -->IpcOutVpss0 --> IpcInVideo0...
View ArticleForum Post: BCP configuration example project for DCI/PDCCH
Hi TI Folks, I have gone through test_lte_dl.c which provides BCP headerconfiguration for dlsch.is there any BCP example project for DCI/PDCCH having header configuration for...
View ArticleForum Post: RE: tlv320aic3106's device and base address
Hi, See, from the datasheet link below, under I2C Control Mode. http://www.ti.com/lit/ds/symlink/tlv320aic3106.pdf-kel
View ArticleForum Post: RE: C6678 Ethernet UDP payload size
I understand the the C6678 can send large packets. My question was explicitly about the EVM6678L.Is there anything in this device that would prevent large packets getting out or is there no limit...
View ArticleForum Post: RE: No source available(DM3730)
Sida,This is not an error. Its try to disassemble the instruction at the address given and looking for a source file. If it can find a source file corresponding to the address, it will display it other...
View ArticleForum Post: RE: Problems runing the "dvsdk_dm3730-evm_4_02_00_06_setuplinux"...
Hi Steve,There are two ways to resolve this. Either reduce kernel memory allocated by changing the bootargs "mem=" or change the parameters to cmemk.ko module in such a way that it doesn't fall under...
View ArticleForum Post: RE: AM/DM3730 and TVP5151 Interlacing Issues
Matthew,This is very difficult to solve over forum.If you can spare one hardware and schematics, I can get it resolved.
View ArticleForum Post: RE: ISP does not synchronize on subsequent frames when missing...
Michael,Ideally ISS should synchronize on next VS. Is this happening every time or once in a while? An immediate work around that you can try is that, to delay enabling ISS so that it starts only after...
View ArticleForum Post: c55xx - sop timer in emulator when the BP occurs
Hi all,I am looking for way to stop the timers when the BP achieved.Unfortunately, I did not found the way in HW (is it true?).Is there a way using GEL (something like gating timers clock in BP)?Thanks...
View ArticleForum Post: RE: SPI0 in kit C6748LCDK
I've only used the LCDK to validate my SPI code without actually talking to a SPI device. I vaguely remember I had HW conflicts that stopped me from using the SPI ports for testting. I checked the LCDK...
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