Sorry we need to clean the docs up a bit here, there are legacy references to srv_clk that need to be replaced. My current understanding is below, but I’m still waiting on confirmation from design. My only issue is that I can’t get the Discovery timer value in mS to work out with the below equation.
The discovery timer is set by the PLM_SP(n)_DISCOVERY_TIMER register. ( Note: Values of 0 & 1 are not legal.) Discovery timer Interval is IP_CLK period X 52429 X DISCOVERY_TIMER. For rev 2.0 silicon, the IP_CLK is either a) the internal DMA clock used by the peripheral which is hard coded to CPU fequency/3 or b) it is the fastest of the Serdes based TXBCLKs(1/20th the data rate, i.e. 2.5Gbaud the Serdes TXBCLK is 125Mhz). The selection of which clock to use here is based on SYS_CLK_SEL and SYS_CLK_VBUSP in the RIO_PER_SET_CNTL1. On pre 2.0 silicon, the IP_CLK is always case b above. Best performance is using case a above.
Note also that the RIO_IP_PRESCAL needs to be set correctly for the silence and discovery timers to have the correct values.
I'll provide more info as I get it.
Regards,
Travis