Brijesh,
No, It can output high and low.but not sync to other signal.So the horizontal resolution is not right,always less than 1920.
I set pinmux as the below.
In vps_platformTI816x.c file,
static Int32 Vps_platformTI816xSetPinMux(void)
{
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0814) = 2; //5 tsi1_dclk vout1_b_cb_c3 VIN1_D9
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0818) = 2; //6 tsi1_data vout1_b_cb_c4 VIN1_D10
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x081c) = 2; //7 tsi1_bytstrt vout1_b_cb_c5 VIN1_D11
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0820) = 2; //8 tsi1_pacval vout1_b_cb_c6 VIN1_D12
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0824) = 2; //9 tsi1_pacerr vout1_b_cb_c7 VIN1_D13
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0828) = 1; //10 tsi2_dclk VIN1_D14
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x082c) = 1; //11 tsi2_data VIN0_D20 vin0_de1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0830) = 1; //12 tsi2_bytstrt VIN0_D21 vin0_fld1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0834) = 1; //13 tsi2_pacval VIN0_D22 vin0_vsync1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0838) = 1; //14 tsi2_pacerr VIN0_D23 vin0_hsync1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x083c) = 2; //15 tsi3_dclk vout1_g_y_yc6 VIN1_D4
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0840) = 2; //16 tsi3_data vout1_g_y_yc7 VIN1_D5
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0844) = 2; //17 tsi3_bytstrt vout1_g_y_yc8 VIN1_D6
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0848) = 2; //18 tsi3_pacval vout1_g_y_yc9 VIN1_D7
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x084c) = 2; //19 tsi3_pacerr vout1_b_cb_c2 VIN1_D8
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0850) = 2; //20 tsi4_dclk vout1_hsync VIN1_D15
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0854) = 1; //21 tsi4_data VIN0_D16 vin1_hsync0 vout1_fld
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0858) = 1; //22 tsi4_bytstrt VIN0_D17 vin1_vsync0 vout1_vsync
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x085c) = 1; //23 tsi4_pacval VIN0_D18 vin1_fld0 vout1_b_cb_c8
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0860) = 1; //24 tsi4_pacerr VIN0_D19 vin1_de0 vout1_b_cb_c9
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0864) = 1; //25 tsi5_dclk vout0_r_cr0 vout1_b_cb_c8 vout1_clk
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0868) = 1; //26 tsi5_data vout0_b_cb_c0 vout1_b_cb_c9 vin1_hsync1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x086c) = 1; //27 tsi5_bytstrt vout0_b_cb_c1 vout1_hsync vout1_avid
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0870) = 1; //28 tsi5_pacval vout0_g_y_yc0 vout1_vsync vin1_vsync1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0874) = 1; //29 tsi5_pacerr vout0_g_y_yc1 vout1_fld vin1_fld1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0878) = 2; //30 tsi6_dclk vout1_avid VIN1_CLK1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x087c) = 1; //31 tsi6_data vin0_hsync0
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0880) = 1; //32 tsi6_bytstrt vin0_vsync0
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0884) = 1; //33 tsi6_pacval vin0_fld0
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0888) = 1; //34 tsi6_pacerr vin0_de0
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x088c) = 1; //35 tsi7_dclk vout0_hsync
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0890) = 1; //36 tsi7_data vout0_vsync
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0894) = 1; //37 tsi7_bytstrt vout0_fld
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0898) = 1; //38 tsi7_pacval vout0_avid
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x089c) = 1; //39 tsi7_pacerr vout0_r_cr1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08b4) = 2; //45 tso1_dclk vout1_clk VIN1_CLK0
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08b8) = 2; //46 tso1_data vout1_g_y_yc2 VIN1_D0
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08bc) = 2; //47 tso1_bytstrt vout1_g_y_yc3 VIN1_D1
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08c0) = 2; //48 tso1_pacval vout1_g_y_yc4 VIN1_D2
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08c4) = 2; //49 tso1_pacerr vout1_g_y_yc5 VIN1_D3
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09d4) = 0; //117 vout0_r_cr2 vout0_hsync vout1_g_y_yc2
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09d8) = 0; //118 vout0_r_cr3 vout0_vsync vout1_g_y_yc3
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09dc) = 0; //119 vout0_r_cr4 vout0_fld vout1_g_y_yc4
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09e0) = 0; //120 vout0_r_cr5 vout0_avid vout1_g_y_yc5
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09e4) = 0; //121 vout0_r_cr6 vout0_g_y_yc0 vout1_g_y_yc6
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09e8) = 0; //122 vout0_r_cr7 vout0_g_y_yc1 vout1_g_y_yc7
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09ec) = 0; //123 vout0_r_cr8 vout0_b_cb_c0 vout1_g_y_yc8
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x09f0) = 0; //124 vout0_r_cr9 vout0_b_cb_c1 vout1_g_y_yc9
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0C80) = 0x10;//288 iic1_scl (mode 0, pull-up selected, pull-up enabled)
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0C84) = 0x10;//289 iic1_sda (mode 0, pull-up selected, pull-up enabled)
// Add VOUT1 PinMux by Colin
//clk
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08B4) = 0x1;
//Y2
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08B8) = 0x1;
//Y3
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08BC) = 0x1;
//Y4
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08C0) = 0x1;
//Y5
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x08C4) = 0x1;
//Y6
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x083C) = 0x1;
//Y7
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0840) = 0x1;
//Y8
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0844) = 0x1;
//Y9
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0848) = 0x1;
//C2
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x084C) = 0x1;
//C3
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0814) = 0x1;
//C4
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0818) = 0x1;
//C5
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x081C) = 0x1;
//C6
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0820) = 0x1;
//C7
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0824) = 0x1;
//C8
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0864) = 0x2;
//C9
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0868) = 0x2;
//FID
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0874) = 0x2;
//DE
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0878) = 0x1;
//HS
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x086C) = 0x2;
//VS
REG32(CSL_TI816x_CTRL_MODULE_BASE + 0x0858) = 0x3;
return (FVID2_SOK);
}