Forum Post: RE: Ridgerun gstreamer 0.10 and 1.0 plugins for DM81xx platforms
Hi, The SDK is using glib 2.35.7, you can find the list here:https://github.com/RidgeRun/eval-sdk-dm816x/tree/master/fs/apps-David
View ArticleForum Post: RE: DDR3 Inizialization failure in C6678
Hi Henry,I'm glad that the DDR3 is operating but after reviewing your initialization, I have a few concerns that I wanted to ask about.First, it looks like the values for write leveling initial ratios...
View ArticleForum Post: RE: DM355 color is missing in video output
Are there any other output clocks from the DM355 available for measuring that are derived from the same reference crystal as the clock used for the video encoder? If so are you able to check the...
View ArticleForum Post: RE: C66x CorePac MAR registers configuration
The PCX bit is for enabling/disabling an external memory (from CorePac perspective) as a cache. For example MSMC is an external shared memory. If has cache capability (such as in Keystone II devices)...
View ArticleForum Post: RE: Using XMC and MAR registers - C6678
Daisuke,I replied to the other thread, but I'll go ahead and comment here as well.The PCX bit is for enabling/disabling an external memory (from CorePac perspective) as a cache. For example MSMC is an...
View ArticleForum Post: RE: DM3730 McBSP EXTCLKGATE bit in XCCR
I found some answers and thought I would post in case someone else may benefit in the future.As it turns out, this feature works exactly as expected on McBSP4. I haven't seen it work on McBSP1 but I...
View ArticleForum Post: Can't get audio loopback working.
I'm trying to get the audio loop-back project from http://processors.wiki.ti.com/index.php/C6713DSK_in_CCSv5 (listed as minimal project on the wiki) working. I've follow all the steps and the program...
View ArticleForum Post: RE: Problems about reading data from DSP6678
Eric,I am sorry that I did not provide enough information.1.The PC is regarded as the PCIE RC, and the PCIE EP is a customized board.(The customized board is designed similar to 6678 EVM, and the...
View ArticleForum Post: RE: SPI Clock and Data lines routing / distribution to multiple...
Thanks Sivaraj, the first reference is helpful in better understanding the nature of the SPI Bus and how I can adjust it to compensate for the buffer/routing delays between the master and slave. The...
View ArticleForum Post: RE: EMIF16 boot through FPGA
Thank you for your reply, Rahul, it was very helpful.Yurii
View ArticleForum Post: RE: TMS320C5515 MCP Nandflash & Ram
Hi LucasI am not aware of any MCP packages for flash/RAM supported for this device. I am also not aware of any tests being done internally to validate the device with MCP devices both from boot...
View ArticleForum Post: RE: Porting BIOSPSP audioSample for LCDK6748 and TLV320AIC34
There's more to this story...The bug occurs only if a non "BIOS_WAIT_FOREVER" timeout was specified in the creation of the GIO_Handle for the Tx channel. The GIO_submit() function times out and...
View ArticleForum Post: RE: Help in creating a new project
Hi Prince,Most of the people will prefer windows env for CCS installation and also all the TI DSP packages (example projects) available readily(.exe) for windows but some of the packages were not...
View ArticleForum Post: RE: C6678 DDR3 PLL question
It's a reserved field used for various internal functions. It needs to be in the defined 0001 setting when the SOC is in use. In that state the /2 output divider will be enabled. Regards, Bill
View ArticleForum Post: RE: 66AK2H interconnect
RY,Yes, the will have to go through Bridge 2 and Bridge 3 respectively. These are 256:128b bridges w/ a 1:1 clocking between TeraNet3_C (which EDMA0 resides on) and TeraNet3_A (which AEMIF16 resides...
View ArticleForum Post: RE: Some problem of PCIE inbound address translation of C6678
Dear Mr. Wang,we want to use the TMDSEVM6678LE with the AMC-PCIe Adapter for education and research at our university.Did I understand it correctly? You have build a driver fpr Windows for this DSP...
View ArticleForum Post: RE: Ipc_start() call in main fails with error Hwi already defined
I am not sure what is the meaning of"Check the vectorID for Cpintc in the device data sheet."Would someone look into this. It has been more than a week and no answer yet.
View ArticleForum Post: RE: 6678 SRIO low-level test program
Ganapathi-If we implement a temporary wire loopback between our 6678 and FPGA, we're able to initialize SRIO on the 6678 side. We can see port_ok and send/receive link maintenance requests. But we...
View ArticleForum Post: Capture cropping issue with DM8148
Hi,We have a DM8148 based custom board, with EZSDK_5_05_02_00 and overlay code. We have a HD camera, which is connected to DM8148 using 16bit capture mode.The camera can be configured either 720p/60 or...
View ArticleForum Post: TMS320VC5510 reflow question
I have a mixed lead/lead-free process. The peak reflow temperature is 240C. We are currently using a leaded version of the TMS320VC5510 which is TMS320VC5510AGGWA2 . Are there any inherent internal...
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