Forum Post: RE: 6678 SRIO low-level test program

Ganapathi-

If we implement a temporary wire loopback between our 6678 and FPGA, we're able to initialize SRIO on the 6678 side.  We can see port_ok and send/receive link maintenance requests.  But we still have issues on our FPGA side.  The thread link you give has some excellent suggestions which should help us to debug this.

Thanks.

-Jeff
Signalogic