Forum Post: RE: save cap frames
Create a usecase with the following links:CaptureLink->ipcFramesOut(M3VPSS) -> ipcFramesIn(HOST/A8)/You will then receive the YUV frames on A8. The physical address will be populated. Use mmap to...
View ArticleForum Post: RE: Colour format is missing while encoding the yuv420 video.
(Please visit the site to view this file)Hi Margarita, I have attached the sample video of yuv420 and we have encoded using the OMX encode example present in ezsdk, original...
View ArticleForum Post: RE: SRIO interface issue on C6657
Updates on our case for the benefits of others.From TI:Can you verify that you are running a gel script prior to loading and running the example, and that it is the latest gel...
View ArticleForum Post: RE: DM365 IPNC: ISIF driver problem for YUV Input
Hi,I verified vsync signal. As you mentioned it comes for 34ms.For Ov7955 sensor, I am using VGA _YUV _30fps_ 24MhzPclk register settings provided by Omnivision technologies. I am checking with other...
View ArticleForum Post: GPIO interrupt on C6657
Hi all,I wanted to configure GPIO02 for interrupt event. But I encountered some problems as below.1. When GPIO02 falling edge triggered at one time, it would entry ISR twice(double entry the ISR).2....
View ArticleForum Post: Support for PAL interfacing with C6748 EVM Facedetect Demo...
Hello,I have developed our own customized board, which is moreover same as per C6748 LCDK.And we have added Composite Video Out peripheral and taken its design as per C6748 EVM.And we have NOT...
View ArticleForum Post: RE: Interrupt configuration of SRIO_LoopbackDioisrExampleProject
Hi Alpaslan,yes, it is correct.The event combiner allows the user to combine up to 32 system events into a single combined event. The events 0, 1, 2, and 3 are the events associated with the event...
View ArticleForum Post: RE: Slew rate problems with HPI
Hi Peter,Moving your post to the correct forum, DM64x DaVinci Video Processor . Regards,Shankari
View ArticleForum Post: RE: EZSDK 5.05 2nd stage U-loader freezes when CS0BW set to on
Hi Don,I can boot from UART with CS0BW set to ON and OFF. In first case I can use NAND for data storage, in second case NAND can not be used, but in both cases UART boot is successful. All that with...
View ArticleForum Post: RE: DM814x : termination resistors for DDR3
Avi,I am checking this with the DDR HW experts. Meanwhile, in the below post is attached the DDR3 JEDEC specification (JESD79-3E) which should be used for DM814x device. Is this the same JEDEC...
View ArticleForum Post: RE: DVRRDK linux kernel patches
If you have a myregisteredsoftware.ti.com account to get DVRRDK releases, you will get notified when a new DVRRDK release is available.
View ArticleForum Post: RE: question about create DM8168 chains
Use DEI link in bypass mode instead of scaler link.Each DEI link can output 2 output resolutions and you can use DEI_H and DEI links .Refer the...
View ArticleForum Post: RE: h264 rate control question
Refer ti_tools\codecs\REL.500.V.H264AVC.E.IVAHD.02.00.xx.xx\500.V.H264AVC.E.IVAHD.02.00\IVAHD_001\Docs\H264_Encoder_HDVICP2_UserGuide.pdf for details.
View ArticleForum Post: RE: 8168 enable VDEC_VDIS_ENABLE_IPCFRAMESOUT( video frames A8 -...
You also have to enable enableVideoFrameExport = TRUE in /dvr_rdk/mcfw/src_linux/mcfw_api/usecases/ti81xx/multich_vdec_vdis.cThis configuration is not tested though. Can you indicate what you want to...
View ArticleForum Post: RE: Question about the scale mode of DEI link
This function is not directly supported by DEI.You can either use SWMS link instead of DEI to achieve this or modify DEI link to update the output buffer address before frame processing so that frame...
View ArticleForum Post: RE: How to configure the OSCIN settings for 25 Mhz crystal
Thanks - that explains it well.Many thanks.
View ArticleForum Post: RE: DM816x CPROC equations
Hi, What is output format from DVO2 and HDMI? If it is same, can you please first make sure that CSC in both of these VENCS are configured with the same settings? Once this is done, we just have to...
View ArticleForum Post: RE: SRIO x4 FPGA master direct IO performance
Hi Clinton,I already did it. And what I seen confused me a little because of the payload size. The maximum SRIO payload size is 256 bytes as I know (surely the value describe the whole transmission...
View ArticleForum Post: RE: Pixel Aspect Ratio DM8168
For me DAR (Display Aspect Ratio) is 4:3 or 16:9.SAR (Storage Aspect Ratio) depends on selected Resolution PAL -> 720x576 or NTSC 720x480 or am I wrong ?For encoder we made a extension to set...
View ArticleForum Post: RE: dei video quality lost
Check with attached patch which selects correct scaler coefficients for DEI.Quality issue could be due to wrong scaler coefficient selection.(Please visit the site to view this file)
View Article