Hi Clinton,
I already did it. And what I seen confused me a little because of the payload size. The maximum SRIO payload size is 256 bytes as I know (surely the value describe the whole transmission size). Other thing is that the described situation in sprabk5 is different than the one described by me.
1. The transmission is initiated by the DSP SRIO LSU unit. I use the FPGA to generate direct IO packets.
2. The LSU can generate transmission in one direction at a time. I want to achieve full duplex transmission.
As I described before at 5Gbps x4 link while one direction transmission I get the speed near to the maximum theoretical - 4links x 5Gbps x 0.8 (8/10 coding) = ~2GB/s and I got about 1.7GB/s (because of protocol overhead and fpga packet generation). In all other links and speed configuration I get the maximum expected speed in one direction and full duplex transmissions. Only not at the x4 5Gbps at full duplex.
I'm interested If the maximum throughput in full duplex transmission is possible in the system I described. FPGA is generating the NREAD ans NWRITE packets. Perhaps there is no way to achieve the max throughput in full duplex at highest speed. Or if it is possible, what I'm doing wrong (system concept, missing register configuration)?