Tom S,
There is no downside to your system design. 100MHz is equally valid for the DDR reference clock. The internal PLL can generate the optimum DDR3 frequencies from both.
Use of the internal mux for the PASS PLL input clock is also fully acceptable assuming you are using 100MHz for the reference clock into the core clock PLL. Separate PASS PLL clock is needed if the core clock reference is an odd rate such as 122.88MHz.
Tom J