[quote user="steve zhang"]
1.
Can consumer receive doorbell from producer?
I do two tests one by one.First I map Doorbell reg0 and bit0 to INTDST0,Second I map doorbell reg0 and bit0 to INTDST16.When producer succeed to send data packet and consumer see that data is available,I view the some registers of SRIO like below:
INTDST0
You can see that doorbell[0].ICSR = 0x0000 0001 and RIO_INTDST_DECODE[0] = 0x0000 0001.Can I consider it that consumer has receive the doorbell packet from producer after data is available ?
[/quote]
Yes, that is correct as long as you didn't manually write the ICSR bit locally on the consumer as you indicated earlier in the thread. This is good. The doorbell is reaching the consumer and setting the interrupt bit. Since you are using INTDST0, the RIO_INTDST0_RATE_CNTL register must be written for the interrupt to fire outside of the peripheral. The pacing register needs to be written each and every time the interrupt needs to fire, so write it during intialization before any packets are sent, and then also every time the interrrupt ICSR bit is cleared so the next interrupt can fire.
[quote user="steve zhang"]
INTDST16
Doorbell[0].ICSR = 0x0000 0001. RIO_INTDST_DECODE[16] = 0x0000 0001.
Likely, Does it mean that consumer have receive doorbell from producer?
I think it means. So,I think consumer have succeeded to receiver doorbell from producer.
[/quote]
Yes, same as above, except there is no need to write the pacing register.
[quote user="steve zhang"]
2.
Is it interrupt configuration issue?
My source code with regarding to interrupt configuration have been proved in past example .
My interrupt configuration code is ported from
pdk_C6678_1_1_2_5\packages\ti\csl\example\cpintc .
Among these examples I have also succeed fire interrupt without any problem.So,I think
Interrupt configuration is good and no problem.
[/quote]
If the ICSR bit is set and you the core is not being interrupted, it is definitely an interrupt routing/configuration issue outside the peripheral. You can look at this article and gel debug script for help:
http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices
[quote user="steve zhang"] As to tx LSU completion code ,I can dump,Since once I wait for LSU completion code on producer.it return 1. That means that Transaction Timeout occurred on Non-posted transaction.[/quote]
Not sure why you would see a timeout. So you are saying after you send one data transfer followed by doorbell packet, you are seeing a 0b001 completion code in the RIO_LSU_STAT_REGx register?