Hi Sriharsha, This concerto_a72_inc.mak file was originally added when we were considering adding RTOS support on the A72. However, since that support was never developed and RTOS only runs on the R5F real-time cores, the concerto_a72_inc.mak file was not required and never used. Therefore, it was removed as part of the cleanup effort between these releases. You should be able to migrate without porting those changes. I hope this answers your question. Thanks, Sarabesh S.
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Forum Post: RE: TDA4AL-Q1: concerto_a72_inc.mak is excluded in ti Psdk 09_02_00_05
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Forum Post: RE: AM620-Q1: Ethernet PHY configuration issue.
I located a usb to ethernet adaptor (1000 Mbps) and I get the following (amber light on Rj45 connector stays on): e2e.ti.com/.../4087.U_2D00_Boot_5F00_TI_5F00_25.txt
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Forum Post: RE: TDA4VL-Q1: [different inference results on PC and EVM]
Hi John, I apologize for the delay in response as I was out of office the past week. Answering your highlighted question first - [quote userid="592082" url="~/support/processors-group/processors/f/processors-forum/1381293/tda4vl-q1-different-inference-results-on-pc-and-evm/5286432#5286432"] According to my understanding, when using the app, we will call SDK executable file instead of edgeai-tidl-tool python code. So i use edgeai-tidl-tool to build io.bin and net.bin, use SDK executable file to test. [/quote] I haven't tried it myself, but yes from my knowledge you can run your model using this SDK executable from vision-apps. However, you can also do this using the features from edgeai-tidl-tools (in this case the onnxrt_ep.py file) as described in the documentation - this way still uses the model artifacts generated by the compilation process. I am recommending using this script while you debug your issue, as it easily allows you to enable different logging options and generate traces that will allow us to debug your main issue further. With regards to the debug - I see that on the EVM you are getting the VX_ZONE_ERROR messages which would likely lead to incorrect inference on the target. Can you try running the vx_app_arm_remote_log.out file first (run ./vx_app_arm_remote_log.out & ) and then run the inference again with the debug level set to 2? Best, Asha
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Forum Post: RE: TDA4VM: LDC without distortion
Hi Carlos, Which verions of tuning tool do you have? The latest version is 3.1. [quote userid="592799" url="~/support/processors-group/processors/f/processors-forum/1386359/tda4vm-ldc-without-distortion"]Is there any way to avoid to add the LUT?[/quote] No, the plugin GUI does not have that option. But, you may set all your mesh LUT entries to 0s between your line 10 and line 11. u_dist_m(:)=0; v_dist_m(:)=0;
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Forum Post: PROCESSOR-SDK-AM64X: SDL - Software Diagnostics Library - ESM - Error Sensing Module Functionality
Part Number: PROCESSOR-SDK-AM64X Tool/software: Hi, So, to monitor error over ESM, it is my understanding that we just have to set the errors we want to monitor, the priority of the error. The we can catch those errors in the ESM Callback. There are other SDL Objects/libraries, such as ECC. Is the ECC just for Error Injection, or do I have to setup ECC at all to be able to monitor errors through the ESM. I am only using the MAIN domain at the moment, so I have configured the ESM like the following static SDL_ESM_config esm_config_main = { .esmErrorConfig = {1u, 8u}, /*Error event to be used for self test */ .enableBitmap = { 0x00000380u, 0xfffffffbu, 0x7fffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, }, /**< All events enable: except clkstop events for unused clocks * and PCIE events */ .priorityBitmap = { 0x00000380u, 0xfffffffbu, 0x7fffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, }, /**< All events high priority: except clkstop events for unused clocks * and PCIE events */ .errorpinBitmap = { 0x00000380u, 0xfffffffbu, 0x7fffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, }, /**< All events high priority: except clkstop for unused clocks * and PCIE events */ };
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Forum Post: RE: TDA4VM: LDC without distortion
I cannot recall if I have tried this previously. There is one parameter in output xml file for turning off the mesh LUT. You may edit that line manually. If it works on H/W, then you don't need to use a large LUT with all 0s. A simple dummy LUT in the xml file should be fine. 1 // LDC_CTRL LDC_EN LDC Enable, 0: Disable, 1: Enable 1 // LDC_CTRL LDMAPEN LD Mapping enable, 0: disable, 1: enable 2 // LDC_CTRL DATAMODE Input data mode, 0: UYVY, 1: Y only, 2: YUV420SP, 3: UV only, 4: YUV422SP, 5: Y1+Y2, 6: Y1 + Y2Y3 0 // LDC_CTRL OP_DATAMODE Output data mode, 0: keep UYVY; 1: convert to 420
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Forum Post: RE: AM625: AM625: Main Domain 'UART5' on M4 (09_02_01_06) - low latency polling
Hello John, I would need few pointers here. What is the method of SoC Initialization you have done ? Instead of the default am62-mcu-m4f0_0-fw, you have modified the example by choosing UART5? Is my understanding correct? (Need to go through the file you have attached) If the answer to your first question is SPL and booting via SD Card boot mode, then: Once the kernel shows up, are you running the rpmsg char echo command? If yes can you paste the command here? Looking forward to your responses. Regards, Vaibhav
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Forum Post: RE: TDA4VM: What properties can be set for the extra-controls of v4l2h264enc?
Hello, Sorry for the delay. Here is the patch I was referring to: e2e.ti.com/.../tiL6.1_2D00_media_2D00_img_2D00_vxe_2D00_vxd_2D00_encoder_2D00_Expose_2D00_I_2D00_Frame_2D00_Period_2D00_Control-_2800_4_2900_.patch Can you see if this control is already added as part of the driver in your setup? If not , then see if you can add that control, rebuild the linux sdk, and let me know your results. If that does not work , then the work around would be to hard code the changes in the driver. Let me know your results and I can share these steps if needed. Thanks, Sarabesh S.
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Forum Post: RE: PROCESSOR-SDK-AM335X: Font Rendering Issue
Hi Davis, Could you try the attached UM libraries? All you need to do is extract the folder and copy the files to your filesystem. On my side, I tested on the AM335 SK EVM and GPU was stable. I ran various Qt tests, gles2test 1 and weston based examples were all passing. With regards to Yocto, I made the following change for SDK 6.01 build: Change the git://arago-project.org/git/meta-arago.git to https://git.ti.com/git/arago-project/meta-arago.git in the txt file. Regards, Krunal e2e.ti.com/.../gpu_5F00_libs.tar.gz
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Forum Post: RE: PROCESSOR-SDK-AM335X: Font Rendering Issue
Hi Krunal, Thank you for providing the tarball unfortunately I see many files and this is a bit of a problem. Based on our conversation, you were clear that the gpu glyph fix resides in the gpu user module therefore would you agree that it is sufficient to just copy over libsrv_um.so? I just want to verify that the fix does in fact only reside in the user mode. Please let me know what you think. Thank you, Davis
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Forum Post: RE: TDA4VM: GPIOMUX_INTRTR0_MUXCNTL vanished from SPRUIL1B (9.9.9.2.2) to SPRUIL1C. Intended or mistake?
Hi Wolfgang, It seems like what you are saying is correct, not sure why the register was left off in the new spruil1c registers. I will look into this and get back to you. I believe the address 0x00A0 0004h is correct for GPIOMUX_INTRTR0_MUXCNTL_n register as the GPIOMUX_INTRTR0_INTR_ROUTER_CFG base address matches in spruil1c at 0x00A0 0000h. Thanks, Neehar
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Forum Post: RE: TMS320C6655: Black Hawk debugger, not detecting
Hello, What is the TI EVM board being used here? Have you tried this on a different board? Thanks
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Forum Post: RE: AM6548: Using PRU pins as GPIO
What is even more strange is that CAP_VDDA_1P8_IOLDO0 is at 1.8V, and CAP_VDDA_1P8_IOLDO_WKUP is at 2.9V. We are attempting to use 3v3 logic for the corresponding VDDSHVx banks. On the IDKEVM, all these signals are sitting around 1.26V. Are they configurable in software somehow? Or through some resistor selection? We are not sure what would cause this discrepancy.
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Forum Post: RE: CCSTUDIO: Switch chip in sdk example project
Hello, Is the issue only specific to this project (and other sysconfig projects do not have this issue)? Also provide the CCS version, sysconfig version, and SDK version being used. Thanks ki
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Forum Post: RE: CCSTUDIO: Switch chip in sdk example project
Also specify the SDK example you are working with. Thanks ki
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Forum Post: RE: CCSTUDIO: Incorrect sizes displayed in the Expressions tab
Hello, I will need to try this out on an F28x target. I do not have one at the moment so I will need to access one before trying this out. I will let you know when I have an update. Thanks ki
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Forum Post: RE: J784S4XEVM: Image flash in J784S4XEVM using Uniflash failing ! or Partial success sometimes
Hi, Can you provide the command you are executing? Thanks, Neehar
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Forum Post: RE: TDA4VM: Write to 00A0 0004h from C66xx_0 not possible
Hello, Could I get some clarifications on what you are trying to achieve? From my understanding you are trying to write to an address within the A72 compute cluster space from the C66x core? Based on the information you have provided I do have a few follow ups - [quote userid="129474" url="~/support/processors-group/processors/f/processors-forum/1386242/tda4vm-write-to-00a0-0004h-from-c66xx_0-not-possible"]I can modifiy the Address-Space ( 0x60000004) in Memory Browser of CCS ! [/quote] Are you doing this from the C66x core or from the DAP port? [quote userid="129474" url="~/support/processors-group/processors/f/processors-forum/1386242/tda4vm-write-to-00a0-0004h-from-c66xx_0-not-possible"]translationCfg4Test3PurposeOnly.translatedAddress = 0x00A00000; // GPIOMUX_INTRTR0_INTR_ROUTER_CFG[/quote] Do note that this 0x00A00000 address maps to the ARMSS_RAT_REGION0 in the R5F memory map - not C66x Best, Asha
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Forum Post: RE: TDA4VH-Q1: DDR signal eye diagram (scope) on TDA4VH EVM and AM69 SK EVM
No - I don't think we have anything customer friendly to show small performance differences between designs.
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Forum Post: RE: CCSTUDIO: Build steps are very slow roughly 3 minutes
Hello, Please see this post regarding slow builds on debian: https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1377853/msp430f4783-ccs-12-slow-to-generate-code-for-msp430f4783/5286855#5286855 Thanks ki
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