The most convenient one I saw was TP18 as it is through hole. However, there are many on the board if you look at the schematic. Thanks, Neehar
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Forum Post: RE: J722SXH01EVM: Unable to connect to XDS110 in CCS
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Forum Post: RE: TDA4VE-Q1: onnxruntime compilation on SDK 9.2 QNX
There are no immediate plans. The TI OpenVx layer is recommended access method to enable TIDL on SDK QNX. Regards, kb
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Forum Post: RE: PROCESSOR-SDK-AM64X: Packet loss occurs when using the Packets HSR Offload solution for forwarding
Hi Tianyi, Thanks for confirming your requirements and the details of the cut-through latency setup. According to the email sent to you and your team, our firmware expert is asking for the following test result from your team. Please give that a try and let us know if you see the same issue as before or not. Residence time at 100Mbps (400B ~39.256us and 1300B ~111.211us): The interface for enabling cut-through mode is separate for the 2 directions eth1->eth2 and eth2->eth1. Please try with below command to enable cut-through mode: (sets bit 0 and bit 8) devlink dev param set platform/icssg1-eth name cut_thru value 257 cmode runtime The firmware version with the fix for the packet loss at 100Mbps was provided in the same email by our firmware expert. -Daolin
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Forum Post: RE: TMS320C6678: Unable to Run STM based Hardware Trace Analyzer
Sorry for the delay. Engineering has responded with the below replies: [quote userid="41338" url="~/support/processors-group/processors/f/processors-forum/1373494/tms320c6678-unable-to-run-stm-based-hardware-trace-analyzer/5271104#5271104"] Does this JTAG and h/w trace with EMU0/1 to multiple devices actually work? Has this been demonstrated to be a viable implementation? Is there other h/w design documentation that we should be looking at? If so, please share that with us. [/quote] [CCS Engineering] We are unsure of this detail. It is possible the device experts may know [quote userid="41338" url="~/support/processors-group/processors/f/processors-forum/1373494/tms320c6678-unable-to-run-stm-based-hardware-trace-analyzer/5271104#5271104"]How can we get these various masters to be shown and selectable within these graphs?[/quote] [CCS Engineering] If they are not in the graphs then no data was collected for those masters. It could be that there were non transaction in the time window data was collected. [quote userid="41338" url="~/support/processors-group/processors/f/processors-forum/1373494/tms320c6678-unable-to-run-stm-based-hardware-trace-analyzer/5271104#5271104"]What does Timing (Ticks) mean?[/quote] [CCS Engineering] This is the bus clock. [quote userid="41338" url="~/support/processors-group/processors/f/processors-forum/1373494/tms320c6678-unable-to-run-stm-based-hardware-trace-analyzer/5271104#5271104"] I s there a way to configure an external trigger during h/w Trace? How is the EMU Trigger Filter used within Advanced Properties? [/quote] [CCS Engineering] This may be possible. We will need to investigate.
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Forum Post: RE: TDA4VL-Q1: On SDK 9.2, Fail to set voltage on Buck 2
Hi Wilson, Thank you for this information. I will look into this further and get back to you. Thanks, Neehar
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Forum Post: RE: AM6442: DMSS what determines which ring a PSI-L channel is associated with on the AM6442?
Hopefully this helps anyone else reading this. We did some more testing, and this is what we confirmed via experiment. PKTDMA CHANNEL NUMBERS: - The valid channel numbers for CPSW_TX_CHAN are 16 to 23. We were able to transmit using any of them. - The only valid channel number for CPSW_RX_CHAN is 16. No other channels would work for CPSW RX. PKTDMA RING INDEXES: - The valid PKTDMA ring indexes for CPSW TX ( CPSW_TX _RING_IDX ) are anything in the range of 16 to 79. We were able to transmit using any of them. But there is an additional constraint in that each TX channel number (CPSW_TX_CHAN) is limited to a block of eight ring indexes. The ring indexes for each channel must obey the following constraint... CPSW_TX_RING_IDX = (16 + (CPSW_TX_CHAN - 16) * 8) TO (23 + (CPSW_TX_CHAN - 16) * 8) - The valid PKTDMA_RING indexes for CPSW Ethernet RX are anything in the range of 128 to 143. Any values in that range appeared to work. CPSW_RX_RING_IDX = 128 to 143 PSIL THREADS: The PSIL threads are set up by the DMSC using the TISCI_MSG_RM_PSIL_PAIR message. For CPSW we found the following thread numbers to work. For TX, the source threads appear to be mapped one to one with the channel numbers. The valid PSI-L thread numbers for TX are. TX_SOURCE_THREAD = 0x1000 + CPSW_TX_CHAN Since the valid channel numbers are 16 to 23 this means that the valid TX PSI=-L thread numbers are 0x1010 to 0x1017 for CPSW. There appears to be only one valid TX destination thread number 0xC500. TX_DESTINATION_THREAD = 0xC500 For RX there appears to be only one valid source thread number 0x4500. RX_SOURCE_THREAD = 0x4500 The RX destination threads seem to follow the same logic as the TX source threads in that the valid number is a base number 0x9000 plus the channel number. But since there is only one RX channel there is only one valid number 0x9010. RX_DESTINATION_THREAD = 0x9010 PKTDMA RX FLOW INDEX: For CPSW RX the valid CPSW_RX_FLOW_INDEX values appear to be determined by which ring index using the following formula. CPSW_RX_FLOW_INDEX = (CPSW_RX_RING_IDX - 128 + 16) Any values matching that formula seemed to work and any values not matching it resulted in dropped packets. The same FLOW_INDEX had to be used in the TISCI_MSG_RM_UDMAP_FLOW_CFG message and the TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG message when setting up the flows using the DMSC. The CPSW determines the flow index based on Ethernet port number, priority and the CPSW_P0_FLOW_ID_OFFSET_REG. Assuming everything else maps to the value 0, just setting CPSW_P0_FLOW_ID_OFFSET_REG equal to CPSW_RX_FLOW_INDEX will work. Note that if the flow index generated by the CPSW block doesn't match the DMA flow index for the RX channel (16) then the DMA will drop the packets. If the flow index programmed in the DMA for that channel doesn't match the index in the packet coming out of the CPSW port 0 then the packets will be dropped. When packets are dropped you can see it in the DMASS0_PKTDMA_0_RFLOWFWSTAT or in the DMASS0_PKTDMA_0_RCHANRT_DCNT registers. It would be nice to see some concise official documentation confirming all this.
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Forum Post: RE: TDA4AL-Q1: TDA4AL88TGAALZRQ1 Power supply designing using TPS6495-Q1
Hello Anusha, For the TDA4AL, the recommended solution for any new designs would be one of the universal PDN-3x solutions that utilizes a single TPS6594133A PMIC. PDN-3A and PDN-3F are two of the more popular solutions. Details can be found in this user guide: https://www.ti.com/lit/pdf/slvuci2
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Forum Post: RE: PROCESSOR-SDK-AM335X: Request for Support: AM335x Processor DDR Memory Upgrade and Configuration
Since you can get regular u-boot working, i don't think this is a DDR issue. Sounds like you have the correct DDR configuration. Sorry i don't know what falcon boot is, i'll have to pass this to the software team. Regards, James
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Forum Post: RE: SK-AM62: Unable to Access SPI Interface from 40-Pin Expansion Connector on AM62xx EVM Running Debian OS
[quote userid="612129" url="~/support/processors-group/processors/f/processors-forum/1380850/sk-am62-unable-to-access-spi-interface-from-40-pin-expansion-connector-on-am62xx-evm-running-debian-os/5296115#5296115"]Now, I would like to enable the SPI2 channel in the EXPANSION HEADER of 40 pin. I need to enable both spi0 and spi2. Is there a straightforward and proper method to do this? [/quote] You can follow what was done in this post here and edit the DTS source file accordingly: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1249053/am625-testing-spi-interface-on-am625-based-custom-board/4752269#4752269 It shows how to setup both the needed pinmux and additions needed to enable the main_spi2 node. Regards, Andreas
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Forum Post: RE: AM625: Delay between two SPI words and CS to first data
Hi Siva, what SDK version are you using? If I recall correctly you need at least SDK v9.1 for DMA to work together with main_spi0 correctly. Please confirm your SDK version. If this isn't the issue, can you post your entire boot/kernel log? Regards, Andreas
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Forum Post: RE: Processors forum
Let me check internally, and get back to you. Best, -Hong
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Forum Post: RE: PROCESSOR-SDK-AM64X: HSR TAG and VLAN TAG order Question
Hi Tianyi, I wanted to check in this, can you provide information on the comments in my previous response here? -Daolin
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Forum Post: PROCESSOR-SDK-AM57X: Issues cloning the OMAP boot repo
Part Number: PROCESSOR-SDK-AM57X Other Parts Discussed in Thread: AM5728 Tool/software: We have a customer who is using a AM5728 SOC on our AM57 SOM and they're utilizing the BSP-Yocto-TISDK-AM57xx-PD20.1.3 and are currently having trouble cloning the OMAP boot repo. They have confirmed that the ROM boot loader is being initialized by the fact that when they connect to their host they can find the device on their Windows device manager but they're unable to connect to the network. Have you come across this issue before and do you have any recommendations on how to clone this repo? Also, do you have any boot loader guides for Windows users? This is the error the customer's seeing when trying to pull repo $ git clone git://git.omapzoom.org/repo/omapzoom.git Cloning into 'omapzoom'... fatal: unable to connect to git.omapzoom.org: git.omapzoom.org[0: 198.47.23.31]: errno=Connection timed out git.omapzoom.org[1: 64:ff9b::c62f:13a7]: errno=Network is unreachable
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Forum Post: RE: AM67A: MMALIB - Examples with FFT
Hi Darren, FFT functionality would be covered in our FFTLIB offering rather than MMALIB. The plan for the 10.0 SDK release is to have FFTLIB as a SDK component for AM67A/J722S - however this will only have a C7x only implementation, and will not have usage of the MMA for the algorithm. Currently, the implementation that utilizes the MMA is supported in our SDKs on our 512-bit C7x variant devices (C7100 and C7120) which are present on J721E, J721S2, and J784S4. Best, Asha
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Forum Post: RE: [FAQ] How to enable switching capability between GPO and GPI operation for PRU GPIO?
Additional Note : Unlocking the CTRLMMR protection mechanism and bidirectional configuration is a one time setup and can be added on R5F side as below. #define KICK0_UNLOCK_VAL (0x68EF3490U) #define KICK1_UNLOCK_VAL (0xD172BC5AU) #define CSL_MAIN_LOCK0_KICK0_OFFSET (0x1008) #define CSL_MAIN_LOCK1_KICK0_OFFSET (0x5008) void config_CTRLMMR() { uint32_t baseAddr; volatile uint32_t *kickAddr; volatile uint32_t *regAddr = (volatile uint32_t *)((uint32_t)0x43004100); baseAddr = (uint32_t)(0x43000000); /* Lock 0 */ kickAddr = (volatile uint32_t *) (baseAddr + CSL_MAIN_LOCK0_KICK0_OFFSET); CSL_REG32_WR(kickAddr, KICK0_UNLOCK_VAL); /* KICK 0 */ kickAddr++; CSL_REG32_WR(kickAddr, KICK1_UNLOCK_VAL); /* KICK 1 */ /* Lock 1 */ kickAddr = (volatile uint32_t *) (baseAddr + CSL_MAIN_LOCK1_KICK0_OFFSET); CSL_REG32_WR(kickAddr, KICK0_UNLOCK_VAL); /* KICK 0 */ kickAddr++; CSL_REG32_WR(kickAddr, KICK1_UNLOCK_VAL); /* KICK 1 */ CSL_REG32_WR(regAddr, 0x0000007F);
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Forum Post: RE: PROCESSOR-SDK-AM64X: Packet loss occurs when using the Packets HSR Offload solution for forwarding
Hi Tianyi, As discussed in the meeting today, I went asked the development team about whether the cut through configuration with queue1 and queue8 is a required configuration for cut-through functionality. Here is the feedback: To enable cut-through forwarding in both directions, cut-through will need to be enabled on both slice0 and slice1 The devlink command to enable cut-thru takes a u16 value. all 16 bits of it represents queues. 8 for slice0, 8 for slice1. BIT 0 to BIT7 are slice0 queues, BIT 8 to BIT 15 are slice1 queues. This is why bit0 and bit8 need to be configured for cut-through with devlink command to configure queue1. I think the confusion might be that setting bit0 and bit8 does not mean setting queue1 AND queue8. It just means queue1 is set for slice 0 and queue1 is set for slice 2 to enable cut-through in both directions. Example, if you need to enable cut-thru on q0 and q1 for both slice 0 and slice1, you need to pass u16 value with BIT 0,1, 8,9 set i.e. you have to pass "0000 0011 0000 0011" = 771 in decimal. We will update this in https://software-dl.ti.com/processor-sdk-linux-rt/esd/AM64X/latest/exports/docs/linux/Foundational_Components/PRU-ICSS/Linux_Drivers/PRU_ICSSG_Ethernet_Switch.html in the future. What changed in the most recently shared firmware and the original firmware? "We recently shifted to 333MHz for ICSSG, so that was creating issues for cut-throguh mode - fixed it in firmware. (This will result in increased residence time for 1G cut-through, 100M/10M remains same as before)." -Daolin
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Forum Post: RE: OMAPL138B-EP: Is there an alternative SoC to OMAPL138?
Please work with local sales/field team on roadmap discussions under NDA. On AM62A AI accelerators - yes customer can use it. Please refer following links to learn more - https://www.ti.com/product/AM62A7 Ti.com/edgeai
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Forum Post: RE: DRA829J: Setting PSDK 9.02.00 environment
Hi José, Yes, your environment you have set up will be enough for MCU development. Thanks, Neehar
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Forum Post: RE: AM625: How to integrate the DLP7970ABP with the AM62xx-EVM using the SPI interface.
Hi Abhijeet, [quote userid="583145" url="~/support/processors-group/processors/f/processors-forum/1369804/am625-how-to-integrate-the-dlp7970abp-with-the-am62xx-evm-using-the-spi-interface/5287051#5287051"]I had a look at NFCLink Firmware but there also it only instructs on how to port to other MSP430s and not any other MCU , so can NFCLink be really set up for AM625 ?[/quote] You don't need this firmware in the context of Linux, the Kernel has a driver already and this is what handles the low-level interface, and we are already using it. In fact this very driver is also pointed to by the related software product folder on ti.com, see https://www.ti.com/tool/TRF7970ASW-LINUX [quote userid="583145" url="~/support/processors-group/processors/f/processors-forum/1369804/am625-how-to-integrate-the-dlp7970abp-with-the-am62xx-evm-using-the-spi-interface/5287051#5287051"] Also , Here's All the signal captures i am getting while booting up , Hope it helps in identifying the problem , what's the expected behaviour ? because i don't think this is ideal. [/quote] I think the interesting part here really is what's shown around the 3s mark. You can see all data/clock signals toggling, which means the TRF device is receiving communication from the AM62x (so pinmux and SPI setup etc. seems to be mostly okay), and it also sends data back, that means it "understands" the communication. But I think you'd want to zoom into this section and decode the traces (should be easy to do with the logic analyzer) to confirm and make sure there is meaningful data being exchanged. Also, in an earlier post you reported "trf7970a_probe: success" in your kernel log, so I think for now we can assume that the low-level setup is probably/mostly okay. But I did some more research and also talking to a colleague that had some NFC background and he pointed me to that we should be using the `neard` low-level NFC stack, which is really what will connect with the low-level device driver, and it also provides some test scripts for userspace (in Python) to work with NFC cards. We have an older application note for an older device (AM335x) on ti.com you can review, see https://www.ti.com/tool/LINUX-NFC-TRF7970A While the steps do not apply to AM62x (do not try them as-is!), the general principle still applies. There's a newer/improved `neard` stack available now, and the latest development can be found at https://github.com/linux-nfc/neard . It actually includes all the improvements/fixes that the solution discussed here https://www.ti.com/tool/LINUX-NFC-TRF7970A provides using a "special" git tree, plus other improvements. I spent some time trying to get this stack to build and integrated into a Linux filesystem image for AM62x but I'm battling some dependency issues in Yocto around Python 3 and other stuff that I wasn't able to fully resolve those yet, but I'll continue working on it. Once I get this stack operational I will share some steps for you to re-create this. And then we'll see what happens trying to use the included userspace test tools/scripts. Regards, Andreas
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Forum Post: RE: PROCESSOR-SDK-AM62X: AM62x-SK-AVM Unable to connect to the network (when connected to 10BASE) Problem inquiry
Hi, We need to verify some data points that you provided. [quote userid="609041" url="~/support/processors-group/processors/f/processors-forum/1386032/processor-sdk-am62x-am62x-sk-avm-unable-to-connect-to-the-network-when-connected-to-10base-problem-inquiry"]ccording to Table 3-19. Default Strap Setting of CPSW Ethernet PHY in the User's Guide AM64x/AM243x Evaluation Module, the setting value for RGMII TX Clock Skew is 2 ns.[/quote] I see you mentioned the AM64 SDK but you are using the AM62 EVM, could you please provide which one you are using? If you are using the AM62 then you will need to use the AM62 SDK. Is the software you are trying to RTOS or Linux? Best Regards, Schuyler
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