Shyam, I'm back from vacation, and so I've been catching up on your previous thread and this thread. Good comments from Sekhar regarding the mechanism by which the device goes to sleep. One area in particular that I think I misconstrued previously related to precisely which code should be executing from internal SRAM. Initially my thought was that the davinci_pm_suspend function should be executing from internal SRAM. On reviewing everything again, I see that's not the case. The davinci_pm_suspend function is only touching the CPU PLL, and that can happen from internal or external RAM. Along similar lines, I made a note in the previous thread that I didn't see the code that handles the DDR PLL. Sekhar gave me the missing piece in that respect, i.e. I needed to look at the davinci_cpu_suspend function inside arch/arm/mach-davinci/sleep.S. I see that function is handling the suspend/resume of the DDR controller and the DDR PLL. In summary: You made some changes to davinci_pm_suspend where you attempted to add some of the DDR handling. Please revert those changes. They are already being done by davinci_cpu_suspend. Can you please try stepping into davinci_cpu_suspend with JTAG? Another option might be to add an assembly spin loop in davinci_cpu_suspend. Once you get there, I'd like you to look at the Program Counter address to verify you're in internal RAM. Another test is it put an assembly spin loop after the "Wake up from sleep" comment in davinci_cpu_suspend. For starters, do NOT connect any JTAG. I want you to get the OMAP-L138 fully to sleep. Wake up the device. It should stick in the assembly spin loop in internal RAM. Connect with JTAG. Verify you're in the assembly spin loop in davinci_cpu_suspend. I think you can add a spin look by doing something like: spin: b spin Best regards, Brad
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Forum Post: RE: Linux/OMAPL138B-EP: how to link code to internal memory in Linux
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Forum Post: Linux/TDA2EXEVM: CAPTURE: VIP Set Params IOCTL Failed
Part Number: TDA2EXEVM Tool/software: Linux Hi there, below is my single camera use-case, which captures , VPE, encode and write to shared memory, Capture -> VPE -> Encode -> IPCIn -> (LINK writes to SM) In this, there is no compile time errors. But i am facing the below issue while running it on the board. ----------------------------------------------------------------------------------------------------------------------------------- [HOST] [IPU2 ] 128.385347 s: CAPTURE: Create in progress !!! [HOST] [IPU2 ] 128.385743 s: CAPTURE: VIP1 Slice0 PortA capture mode is [ 8-bit] !!! [HOST] [IPU2 ] 128.386353 s: captdrv/src/vpsdrv_captureCore.c @ Line 335: [HOST] [IPU2 ] 128.386445 s: Set VIP parameter failed [HOST] [IPU2 ] 128.386506 s: CAPTURE: VIP Set Params IOCTL Failed!!! [HOST] [IPU2 ] 128.386567 s: CAPTURE: WARNING: Create args numBufs[0] < min[4]. Overriding create args !!! [HOST] [IPU2 ] 128.389709 s: CAPTURE: Create Done !!! [HOST] [IPU2 ] 128.390197 s: VPE: Create in progress !!! [HOST] [IPU2 ] 128.521228 s: vpecore/src/vpscore_vpeCommon.c @ Line 408: [HOST] [IPU2 ] 128.521350 s: Data format (224) not supported!! [HOST] [IPU2 ] 128.521442 s: vpecore/src/vpscore_vpeCommon.c @ Line 459: [HOST] [IPU2 ] 128.521533 s: Width(1)/StartX(0) can't be odd!! [HOST] [IPU2 ] 128.521625 s: vpecore/src/vpscore_vpeApi.c @ Line 453: [HOST] [IPU2 ] 128.521686 s: Invalid Parameters!! [HOST] [IPU2 ] 128.521777 s: vpedrv/src/vpsdrv_m2mVpeCore.c @ Line 917: [HOST] [IPU2 ] 128.521838 s: Set params for VPE core failed! [HOST] [IPU2 ] 128.521960 s: vpecore/src/vpscore_vpeApi.c @ Line 642: [HOST] [IPU2 ] 128.522052 s: Set the parameter before getting the descriptor info!! [HOST] [IPU2 ] 128.522143 s: vpedrv/src/vpsdrv_m2mVpeCore.c @ Line 927: [HOST] [IPU2 ] 128.522235 s: Could not get context info for VPE core! [HOST] [IPU2 ] 128.522326 s: vpedrv/src/vpsdrv_m2mVpeCore.c @ Line 245: [HOST] [IPU2 ] 128.522418 s: Config of core 0 for channel 0 failed. [HOST] [IPU2 ] 128.522509 s: vpedrv/src/vpsdrv_m2mVpeApi.c @ Line 908: [HOST] [IPU2 ] 128.522601 s: Configuring of cores failed [HOST] [IPU2 ] 128.522662 s: Assertion @ Line: 713 in vpeLink_drv.c: retVal == SYSTEM_LINK_STATUS_SOK : failed !!! ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Any advise would be helpfull, Regards Balaji T
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Forum Post: Linux/AM3505: NETDEV WATCHDOG: wwan0 (qmi_wwan): transmit queue 0 timed out
Part Number: AM3505 Tool/software: Linux Hi All, Processor part number : AM3505 Kernel : 2.6.37 We are using AM3505 based product from long time. We are using different types of USB modems in our product for streaming purpose. From last couple months we are experiencing strange issue. While streaming continuously from the device it get following crash. [ 8604.721832] NETDEV WATCHDOG: wwan0 (qmi_wwan): transmit queue 0 timed out [ 8604.730346] Modules linked in: act_mirred sch_ingress cls_u32 sch_prio xt_mark g_mass_storage ifb xt_conntrack wl12xx_sdio wl12xx mac80211 cfg80211 compat qmi_wwan cdc_wdm tun rndis_host cdc_ether dieid(P) cdc_acm sierra qcserial option usb_wwan usbserial ppp_async ppp_synctty ppp_generic slhc nfsd exportfs [last unloaded: g_mass_storage] [ 8604.809692] [ ] (unwind_backtrace+0x0/0xec) from [ ] (warn_slowpath_common+0x4c/0x64) [ 8604.820922] [ ] (warn_slowpath_common+0x4c/0x64) from [ ] (warn_slowpath_fmt+0x2c/0x3c) [ 8604.832336] [ ] (warn_slowpath_fmt+0x2c/0x3c) from [ ] (dev_watchdog+0x144/0x22c) [ 8604.843200] [ ] (dev_watchdog+0x144/0x22c) from [ ] (run_timer_softirq+0x13c/0x1d8) [ 8604.854248] [ ] (run_timer_softirq+0x13c/0x1d8) from [ ] (__do_softirq+0x74/0xfc) [ 8604.865112] [ ] (__do_softirq+0x74/0xfc) from [ ] (irq_exit+0x40/0x8c) [ 8604.875000] [ ] (irq_exit+0x40/0x8c) from [ ] (asm_do_IRQ+0x78/0x98) [ 8604.884674] [ ] (asm_do_IRQ+0x78/0x98) from [ ] (__irq_svc+0x34/0x80) [ 8604.894439] Exception stack(0xc0591f80 to 0xc0591fc8) [ 8604.901123] 1f80: 00000000 40000013 40000013 00003505 c0590000 c05d0900 c002e36c c059401c [ 8604.911071] 1fa0: 8002c954 411fc087 0000001f 00000000 c05a3b60 c0591fc8 c0087128 c0087738 [ 8604.921051] 1fc0: 60000013 ffffffff [ 8604.926116] [ ] (__irq_svc+0x34/0x80) from [ ] (omap3_pm_idle+0x48/0x4c) [ 8604.936157] [ ] (omap3_pm_idle+0x48/0x4c) from [ ] (cpu_idle+0x48/0x88) [ 8604.946105] [ ] (cpu_idle+0x48/0x88) from [ ] (start_kernel+0x24c/0x2a0) [ 8604.956146] [ ] (start_kernel+0x24c/0x2a0) from [ ] (0x80008034) [ 8604.965454] ---[ end trace 3d7e4faaa8ec4b9d ]--- Sometimes... Following crash but method to reproduce is same. 2019-06-03T16:24:33.452203+00:00 corecard kernel: [ 9453.719726] NETDEV WATCHDOG: eth1 (cdc_ether): transmit queue 0 timed out 2019-06-03T16:24:33.452234+00:00 corecard kernel: [ 9453.726867] Modules linked in: g_mass_storage act_mirred sch_ingress cls_u32 sch_prio xt_mark ifb xt_conntrack wl12xx_sdio wl12xx mac80211 cfg80211 compat qmi_wwan cdc_wdm tun rndis_host cdc_ether dieid(P) cdc_acm sierra qcserial option usb_wwan usbserial ppp_async ppp_synctty ppp_generic slhc nfsd exportfs [last unloaded: g_mass_storage] 2019-06-03T16:24:33.452264+00:00 corecard kernel: [ 9453.758575] [ ] (unwind_backtrace+0x0/0xec) from [ ] (warn_slowpath_common+0x4c/0x64) 2019-06-03T16:24:33.452264+00:00 corecard kernel: [ 9453.768463] [ ] (warn_slowpath_common+0x4c/0x64) from [ ] (warn_slowpath_fmt+0x2c/0x3c) 2019-06-03T16:24:33.452295+00:00 corecard kernel: [ 9453.778533] [ ] (warn_slowpath_fmt+0x2c/0x3c) from [ ] (dev_watchdog+0x144/0x22c) 2019-06-03T16:24:33.452325+00:00 corecard kernel: [ 9453.788085] [ ] (dev_watchdog+0x144/0x22c) from [ ] (run_timer_softirq+0x13c/0x1d8) 2019-06-03T16:24:33.452325+00:00 corecard kernel: [ 9453.797790] [ ] (run_timer_softirq+0x13c/0x1d8) from [ ] (__do_softirq+0x74/0xfc) 2019-06-03T16:24:33.452356+00:00 corecard kernel: [ 9453.807312] [ ] (__do_softirq+0x74/0xfc) from [ ] (irq_exit+0x40/0x8c) 2019-06-03T16:24:33.452386+00:00 corecard kernel: [ 9453.815826] [ ] (irq_exit+0x40/0x8c) from [ ] (asm_do_IRQ+0x78/0x98) 2019-06-03T16:24:33.452417+00:00 corecard kernel: [ 9453.824188] [ ] (asm_do_IRQ+0x78/0x98) from [ ] (__irq_svc+0x34/0x80) 2019-06-03T16:24:33.452417+00:00 corecard kernel: [ 9453.832580] Exception stack(0xcefa5ac0 to 0xcefa5b08) 2019-06-03T16:24:33.452447+00:00 corecard kernel: [ 9453.837890] 5ac0: 00002bd7 ffffffff 000008e8 00000000 0003f420 cf558480 000000bc cab02a80 2019-06-03T16:24:33.452447+00:00 corecard kernel: [ 9453.846496] 5ae0: cf4f3210 00000000 cf4f3010 00000000 0003f420 cefa5b08 c028fd60 c0202700 2019-06-03T16:24:33.452478+00:00 corecard kernel: [ 9453.855102] 5b00: 20000113 ffffffff 2019-06-03T16:24:33.452508+00:00 corecard kernel: [ 9453.858795] [ ] (__irq_svc+0x34/0x80) from [ ] (__delay+0x0/0xc) 2019-06-03T16:24:33.452508+00:00 corecard kernel: [ 9453.866760] ---[ end trace 63ce703603e351f1 ]--- Only solution is to reboot board to recover and again put device on streaming. This issue is not very frequently reproducible. It takes sometimes 2 to 3 hours sometimes complete day. One observation from our side is that we use Audio playback application while streaming this issue took less time to reproduce. Any suggestion or pointers to proceed for this issue will be appreciated. Thanks, Jemish
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Forum Post: AM3352: Why tRAS MAX must be set to 15 in timing 3 register?
Part Number: AM3352 While in DDR3 datasheet, tRAS MAX is 9*tREFI, but in AM335x TRM it is fixed to 15 for DDR3?
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Forum Post: TDA3MA: TDA3 and ISS: Start and End of Frame Timing Expectation
Part Number: TDA3MA (submitted by TI Jason Hale on behalf of an external request) I am using TDA3x and using \starterware_01080124\include\vps\iss library and callback are registered to notify the system when start of frame(embedded header lines) and end of frame (entire image height lines) have been received at the video port. Recently, I saw that end of frame comes in way quicker than expected on a visualization tool sometimes as per snippet short_frame.png . The frame rate is 60fps so the frame should come in every 16msec but now I saw that the end of frame is coming in 4ms after start of frame. I would like to know how are the root causes that can cause this short frame. How can I better handle from video port module so that I do not take in this short frame.
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Forum Post: RTOS/AM5726: LRO or TSO feature for Ethernet
Part Number: AM5726 Tool/software: TI-RTOS Hi, Does AM57xx have LRO (Large Receive Offload) or TSO (TCP Segmentation Offload) feature for Ethernet ? I heard that some processors have it. The customer wants to send 320KB data every 10ms, but it took average 23ms to send 320KB. Do you have any idea to perform 320KB / 10ms ? Thanks and regards, Hideaki
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Forum Post: RTOS/PROCESSOR-SDK-AM437X: Pins configuration
Part Number: PROCESSOR-SDK-AM437X Tool/software: TI-RTOS Hi, I using AM437x based custom board (CCS 6.2 and TI RTOS SDK 3_01_00_06), I am using "GPIO_LedBlink_evmAM437x_armExampleProject" as a project template. I have configured the GPIOs GPIO4_12, GPIO4_13, GPIO4_9, GPIO4_10 and GPIO4_11 as outputs. I have written "HIGH" for all of these GPIOs using the function "GPIO_write" function but only GPIO4_12, GPIO4_13 and GPIO4_11 are reflecting the state "HIGH" (+3.3V) and other two GPIOs are not at all changing the state (always read as 0.2V). Kindly suggest me how to control the other two GPIOs . Also i want use SPIO0 pins CS0, SCLK, D0, D1 as GPIOs , kindly provide the procedure how to configure these pins as GPIOs. Regards Nagaraj G
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Forum Post: CCS/TMDSLCDK6748: LCDK6748 / AIC3106 volume control pop noise
Part Number: TMDSLCDK6748 Tool/software: Code Composer Studio I'm developing an audio program by referring to the McAsp example. My first goal was to bypass the sound that came into Line-in. Also receives input from the mic port to perform some calculations. I wanted to decrease the line-in sound passing bypass according to the calculated results. However, if you use registers 86 and 93 to turn down the sound, pop noise will occur and the sound will be too small, so I looked for another way. The way I thought about it was to store the sound source in memory and bring it back to play. And again this time, I tried to use registers to decrease the sound, but pop noise continued to occur. Is there any way to reduce bypass sound? Or is there a way to decrease sound without pop noise when playing it in the txBuf of the McAsp example? Why pop noise occurs when you decrease the volume?
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Forum Post: AM4379: FAE Support
Part Number: AM4379 Hi E2E, Good day. One of our customer is requesting to come in contact with an FAE. They are interested to know AM4379BZDNA100. The estimated production volume is 10000-15000 2000 per year and is expected to start on Q1 of 2020. Kindly let me know if someone could help and who could help. I will email to the e2e personnel the details of the customer once confirmed. Thanks in advance. Best regards, Art
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Forum Post: CCS/TMS320C6748: EDMA3
Part Number: TMS320C6748 Tool/software: Code Composer Studio I'd like to use EDMA3 on two 16-bit GPIO input data words. After reading about EDMA3, it seems straightforward, but I am not sure whether the volatile aspect of input data may preclude using EDMA3. Specifically, the two 16-bit values are coming from ADS4245 . The goal is to transfer them to memory. My question is if I specify the element size 2, will EDMA3 read the 16 bit quantity so that volatility aspect does not interfere withe correct reading. Please explain. thanks.
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Forum Post: OMAP-L138: Reset DSP core while interprocessor communication
Part Number: OMAP-L138 Hello, I have successfully implemented Interprocessor communications scheme in OMAPL-138. My scheme is mentioned below, 1) ARM gathers some input data from external peripherals. 2) Its writes the data on the separate portion of the shared RAM. 3) ARM generates interrupt on CHIPSIG_3 to DSP. 4) DSP starts executing its ISR (Interrupt Service Routine). 5) DSP reads the data from ISR 6) DSP then perform some FIR algorithm 7) it writes back the output data on shared RAM and clears the CHIPSIG_3 interrupt. My question is what if DSP is hanged in its ISR. Is there any possiblity to reset the DSP core only while it is executing its ISR? Waiting for your prompt reply.
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Forum Post: RTOS/AM4377: Previous (archived) release of processor SDK for legacy projects
Part Number: AM4377 Tool/software: TI-RTOS I need to download some older releases of the PDK. I was given some projects that explicitly require particular versions of PDK - for example "ti/pdk_am437x_1_0_9/packages" is referenced several times in makefile for given project. Attempt to use different (current) PDK fails - some file or folders are missing of moved in a different structure - for example I2C driver sources. I also have even older projects that depend on 1_0_4 PDK version - it would be nice if those (and probably all other archived versions) could be downloaded from some TI server. I found archived documentation for those old versions and this is nice - but I could not locate how to download any of them. Also, I think that it make sense to provide download for Win, Linux and MacOS - I have one of the required PDKs version but for Windows - now I need the same one for Linux and I cannot find where to download it.
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Forum Post: AM3352: SD boot not working, strange behavior of UART boot
Part Number: AM3352 Dear all, i am working on a CPU marked SN150752100BZCZA, i cannot find the whole code in any datasheet, but i am supposing (from the 100BZCZA) it is an AM3352 . I have 2 issues, 1) setting bootstrap configuration for SD boot, using an SD created by sdk create-sdcard.sh, booting i see abt 120msecs of SD clock, but then a fall back to UART boot happens (i get xmodem CCCC sync). MLO and u-boot.img are in the proper fat partition, as created by SDK. 2) trying UART boot, xmodem 1k upload stops at 52224 bytes, so i cannot complete spl u-boot upload (while the CPU should allow 109KB). If any help, welcome. Regards Angelo
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Forum Post: RE: Linux/AM5708: GPIO conflict in AM5708 custom board
[quote user="Jose Carlos Billalabeitia"] As a remainder, the issue was in GPIO6 and it was solved by writing 0x0D20_0000 at CTRL_CORE_CONTROL_PBIAS (address 0x4A00 2E00). We see from time to time that GPIO6 is not working fine and it coincides with the fact that in the above register we see 0x0CA0_0000 instead of 0xD20_0000. There are two bits that change their values when it goes bad. [/quote] Looks to me like 4 bits have changed, 26:23. Bits 26:25 are R/W while 24:23 are read-only. You mentioned previously that you made the following note: [quote user="Jose Carlos Billalabeitia"] I set that register with the same value as the u-boot has (0x0D20_0000) ... ... and finally it worked !!! [/quote] In other words, earlier it seemed like you were able to write to this register. Are you saying on some boards you cannot write to this register? For example: Do some boards exhibit this issue all of the time? Do all/most boards exhibit this issue some of the time? When you encounter the issue, is it seen immediately at boot time, or does the behavior randomly change at some later time?
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Forum Post: RE: OMAP-L138: looking for early boot phase debugging hints
[quote user="Horst Bechtold"] ARM9_0: GEL Output: --------------------------------------------- ARM9_0: GEL Output: | BOOTROM Info | ARM9_0: GEL Output: --------------------------------------------- ARM9_0: GEL Output: ROM ID: d800k008 ARM9_0: GEL Output: Silicon Revision 2.1 ARM9_0: GEL Output: Boot pins: 30 ARM9_0: GEL Output: Boot Mode: Emulation Debug ARM9_0: GEL Output: ROM Status Code: 0x00000000 Description:ARM9_0: GEL Output: No error ARM9_0: GEL Output: Program Counter (PC) = 0xFFFF0000 ARM9_0: GEL Output: [/quote] Horst -- sorry I was on vacation and there's no "out of office" for the forum. Thanks, Rahul, for jumping in. I wanted to highlight the line above from your JTAG script. That line gets output based on the value of the BOOTCFG register. The BOOTCFG register is a read-only register that latches the boot pin state on reset. In your failed case it is latching as "Emulation Debug" mode, i.e. 0x1E. The boot ROM uses this value to determine what to do, so the behavior makes sense. In other words, you need to figure out why your boot pins are latching improperly on the failing boards. Maybe you already have... Can you please update us on whether your issue is resolved?
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Forum Post: RE: CCS/TMS320C6678: Why DSP of TCI6614/6616 Is Much Slower Than Expected
Hello, What is the version of the compiler you are using? What are the compile options? Can you try to adjust complier option for speed? Where do you run the code? Can you try to run in in internal memory? Also something minor: you are looking at the t_overhead value as that is the duration of your function call. best regards, David Zhou
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Forum Post: RE: CCS/TMS320C6657: Underrun or Overflow (UOR) Event triggers are possible as well as potential system lockups when using UPP_2xTXCLK.
Hi Jose Thanks- it is clear that there is some issue with your setup with external clock, as you have this working with internal clock. There are no known issues using external clock and there is very limited description on the failure - can you let me know why using internal clock for this is not an option? Can you further elaborate on the failure - I set up a test that repeatedly rdo 17 different cycles. With an external uPP clock, a uPP transfer always failed (with an underrun or overflow event) before 1000 iterations of the test. Is it an underrun or overflow, does the frequency of failures increase or decrease with clock. You did not share any further inputs on whether you could have some sort of synchronization issues /where you see failures close to start of transfer or somewhere in the middle. Unfortunately with the amount of info we have and limited ability to support uPP , I am not sure how else to close this with you. Sorry for the delays in responding back with the above.
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Forum Post: RE: Linux/DRA745: DRA745 : How to enable audio through HDMI
Chokri, Are you using single or dual display? I'd focus more on the hwmod errors that you're observing at boot time. I suspect it may be preceded by other errors. Do you see the same behavior (hwmod error) without RVC patches in kernel? Regarding EDID parsing, please try the following steps: host# adb pull /sys/devices/platform/omapdrm.0/drm/card0/card0-HDMI-A-1-/edid my_edid host# hexdump -e '16/1 "0x%02x " "\n"' my_edid Then you can use an online EDID parser and check the audio block. BTW, if your goal is to have HDMI audio as primary audio device, you need to recompile Android with the following change in device.mk : PRIMARY_AUDIO := hdmi
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Forum Post: RE: TMS320C6748: Optimize HWI and SWI execution
The MAR bit setting for MAR128 and MAR192-MAR223 indicate that the SHRAM and DDR regions are cached as expected. I would check to confirm when L2 is configured as SRAM in platform configuration. there is information in the platform settings that doesn`t physically change anything on the chip like the CPU frequency. The platform is only a way to inform BIOS Of the platform settings and not necessarily something that updates the core configuration. The BIOS profiling uses on chip timers but also requires BIOS cpu freq to be set correctly as explained here: http://processors.wiki.ti.com/index.php/Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricks#How_to_get_accurate_clock_ticks_from_the_clock_module.3F Make sure you have set the cpuFreq to 375 since the defaults assume 300 Mhz. yOu can also use DSP internal cycles counter TSCL and TSCH just to correlate the data is accurate. Regards, Rahul
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Forum Post: RE: PROCESSOR-SDK-OMAPL138: CSL update breaks project
Hi Friedrich, [quote user="Friedrich Feichtinger26"] OK, so I would have to MANUALLY #include ? This is confusing. How could I know that OMAL138 is using V0 of GPIO? Why do I even have to care about the version? The project already KNOWS that I want to compile for OMAPL138, so why doesn't the CSL handle this automatically? [/quote] Normally you would just need to include the top-level header file ~\pdk_omapl138_1_0_8\packages\ti\csl\csl_gpio.h and define "SOC_OMAPL138" in your project and it would automatically pull the correct version based on the SOC defined, but this is not currently implemented. I've filed a bug to address this issue. Until this is fixed, please manually include the V0 driver. The drivers are split up into different versions to support multiple platforms. Please refer to Table 21-1 of the TRM to see how the pins and banks are defined. GP6P15 is pin 112, so you would do: GPIOPinWrite_v0(CSL_GPIO_0_REGS, 112, GPIO_PIN_HIGH);
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