Part Number: DRA745 Tool/software: Linux Hi, With Jacinto6 DRA74x, 6AO.1.1 ( processors.wiki.ti.com/.../6AO.1.1_Release_Notes) Using - Prebuilt Release Image : software-dl.ti.com/.../index_FDS.html - RobustRVC : Robust_RVC-5.0_Phase-6 (RobustRVC-5.0/rvc_phase-6/emmc_files) - SDK Vision : PROCESSOR_SDK_VISION_03_02_00_00 The HDMI display works fin e but the audio through HDMI is not working. act1000:/ # tinyplay /data/audio.wav -D 1 -d 0 [ 169.637453] omapdss_hdmi5 58040000.encoder: ASoC: can't open interface 58040000.encoder: -1 Regards, Chokri
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Forum Post: Linux/DRA745: DRA745 : How to enable audio through HDMI
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Forum Post: OMAP-L132: Device Cannot be detected in Windows10 when using USB3.0 port
Part Number: OMAP-L132 Hi, regarding this question https://e2e.ti.com/support/processors/f/791/p/801262/2986630#2986630 , sorry for the late reply, been busying with other project. To reply to lding: We are using SBL. Do you have any sample driver code for USB3.0 that works in Windows10? Thanks.
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Forum Post: Linux/AM3359: PRU Remoteproc
Part Number: AM3359 Tool/software: Linux Hello all, I'm working on a custom board based on am335x ice v2.I want to toggle gpio pins at 12MHz.I have learnt that this is not achievable with cortex a8 because of the slow l4 interconnect.We have decided to use PRU cores for achieving this.I want to use Togglegpio application which comes with the SDK.But after booting im not able to see "/sys/class/remoteproc/remoteproc1" and "/sys/class/remoteproc/remoteproc2" in the sysfs entry.However there is remoteproc0.How to enable remoteproc1 and remoteproc2? dts file: (Please visit the site to view this file) Regards, Murugan S
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Forum Post: Linux/AM3359: pru cores remoteproc1 and remoteproc2 not found
Part Number: AM3359 Tool/software: Linux Hello all, I'm working on a custom board based on am335x ice v2.I want to toggle gpio pins at 12MHz.I have learnt that this is not achievable with cortex a8 because of the slow l4 interconnect.We have decided to use PRU cores for achieving this.I want to use Togglegpio application which comes with the SDK.But after booting im not able to see "/sys/class/remoteproc/remoteproc1" and "/sys/class/remoteproc/remoteproc2" in the sysfs entry.However there is remoteproc0.How to enable remoteproc1 and remoteproc2? dts file: (Please visit the site to view this file) Regards, Murugan S
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Forum Post: Linux/TDA2SX: DDR3 test cases or test tool
Part Number: TDA2SX Tool/software: Linux Hi all, 1. Does TI have any DDR3 test cases or test application(like stress tool) to test the DDR3 chip before board bring up?As we are going to change the DDR3 in our custom board. 2. How we will test the DDR3 parameters like wait cycles,Access cycles,temperature etc; Thanks & Regards, A.Kavya Harini.
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Forum Post: Linux/PROCESSOR-SDK-AM335X: Kernel boot hangs on custom board
Part Number: PROCESSOR-SDK-AM335X Tool/software: Linux Hi, We are trying to run u-boot and kernel on the custom board with AM3352 processor. We are using u-boot and Linux available in the latest TI-SDK (TI-SDK-5.03.00.07). For u-boot, we have modified the board configuration as per our board and u-boot is working i.e) we are able to see the u-boot prompt. We have compiled the kernel with default configuration for “tisdk_am335x-evm_defconfig” make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- distclean make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- tisdk_am335x-evm_defconfig make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- zImage We are trying to boot the kernel from u-boot prompt manually with below commands, but the kernel is not coming up. fatload mmc 0:1 0x88000000 am335x-evm.dtb fatload mmc 0:1 0x82000000 zImage setenv bootargs console=ttyS0, 115200 bootz 0x82000000 - 0x88000000 Kernel is not booting below is the message: U-Boot 2018.01-00569-g7b4e473842-dirty (Jun 26 2019 - 17:34:38 +0530) CPU : AM335X-GP rev 2.1 Model: TI AM335x EVM DRAM: 256 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0 Net: No ethernet found. Hit any key to stop autoboot: 0 => fatload mmc 0:1 0x88000000 am335x-evm.dtb 41323 bytes read in 6 ms (6.6 MiB/s) => fatload mmc 0:1 0x82000000 zImage 3912192 bytes read in 332 ms (11.2 MiB/s) => setenv bootargs console=ttyS0, 115200 => bootz 0x82000000 - 0x88000000 ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Device Tree to 8df08000, end 8df1516a ... OK Starting kernel ...We again re-compiled the kernel to generate uImage from below command: make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- LOADADDR=0x82000000 uImage and tried to boot the kernel with below commands, but still we could not. U-Boot 2018.01-00569-g7b4e473842-dirty (Jun 26 2019 - 17:34:38 +0530) CPU : AM335X-GP rev 2.1 Model: TI AM335x EVM DRAM: 256 MiB NAND: 0 MiB MMC: OMAP SD/MMC: 0 Net: No ethernet found. Hit any key to stop autoboot: 0 => => => fatload mmc 0:1 0x88000000 am335x-evm.dtb 41323 bytes read in 6 ms (6.6 MiB/s) => fatload mmc 0:1 0x82000000 uImage 3912256 bytes read in 332 ms (11.2 MiB/s) => setenv bootargs console=ttyS0, 115200 => bootm 0x82000000 - 0x88000000 ## Booting kernel from Legacy Image at 82000000 ... Image Name: Linux-4.14.79-ge669d52447 Created: 2019-06-28 6:51:48 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3912192 Bytes = 3.7 MiB Load Address: 82000000 Entry Point: 82000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 88000000 Booting using the fdt blob at 0x88000000 Loading Kernel Image ... OK Loading Device Tree to 8df08000, end 8df1516a ... OK Starting kernel ... Bootloader can read the Kernel and DTB file from SD-Card but control is not being passed to kernel. (that is what we are presuming). We have refered to below link and looks like that our problem is like Problem #1 explained in below link. http://processors.wiki.ti.com/index.php/Kernel_-_Common_Problems_Booting_Linux#Problem_.232_-_No_more_output_is_seen_on_the_console_after_.22booting_the_kernel.22 . Since our is custom board and is somewhat similar to am335x-evmsk board. We are now suspecting that there may be some problem with respect to .DTB file and now we are looking up generating .DTB file for our board. From the TI PinMux Tool we have generated below files: Am335x_pinmux.h Am335x_pinmux_data.c Devicetree.dtsi From the above generated files, I have below questions: Which are the .h and .c files in the U-boot and Linux needs to be updated using above files? Do I need to update/modify .dts files both in U-boot and Linux also? If yes, please let us know the most nearby/closest file which can be used as reference for this? I am noticing that .dtb file is generated by both both in u-boot and Linux. Which is the file I need to copy to the BOOT folder of the SD-card? Please let us know the steps for creating/modifying the DTS and DTSI file. Also steps to copy the files with details on and folders. Regards Srinivasa
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Forum Post: RE: Linux/AM5728: PRU and DSP shared memory
Hi, The resource table shown in the post is for DSP. I am not sure if PRU uses it. PRU though using remoteproc, but it is implemented separately. Have you seen PRU Remoteproc User's Guide, http://processors.wiki.ti.com/index.php/PRU-ICSS_Remoteproc_and_RPMsg I'll need to involve our PRU expert to see if he has any inside on the shared memory. Rex
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Forum Post: RE: Linux/PROCESSOR-SDK-AM335X: Kernel boot hangs on custom board
Hello Srinivasa, Since your board is am335x-evmsk based. Can you try to boot with am335x-evmsk.dtb ? Best regards, Kemal
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Forum Post: RE: RTOS/TMDX654IDKEVM: Diagnostic examples
Hi Karthik, Yes I'm using 5.03, prebuilt images and j12 port. The icssgEmac test seems to work fine so the cable is ok.
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Forum Post: RE: PROCESSOR-SDK-TDA2PX: An exception occurs when MCAN calls mcan cls module provided by Ti.
Hi Rishabh, The exception issue is resolved. It was causing due to some mismatch in MCAN address. However I can see Can is initialized and we are getting acknowledgement for any RX message we are transmitting through the Canalyzer. But we are not getting any interrupt for Rx as well as Tx. I can see interrupt Enable register are set, I suspect it may be due to Cross bar mapping. I have attached the source files please have a look and let me know if the mapping is correct. (Please visit the site to view this file)(Please visit the site to view this file)(Please visit the site to view this file)(Please visit the site to view this file) Regards, Bikash
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Forum Post: RE: PROCESSOR-SDK-TDA2PX: An exception occurs when MCAN calls mcan cls module provided by Ti.
Hi Rishabh, The exception issue is resolved. It was causing due to some mismatch in MCAN address. However I can see Can is initialized and we are getting acknowledgement for any RX message we are transmitting through the Canalyzer. But we are not getting any interrupt for Rx as well as Tx. I can see interrupt Enable register are set, I suspect it may be due to Cross bar mapping. I have attached the source files please have a look and let me know if the mapping is correct. (Please visit the site to view this file)(Please visit the site to view this file)(Please visit the site to view this file)(Please visit the site to view this file) Regards, Bikash
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Forum Post: RE: PROCESSOR-SDK-TDA2PX: An exception occurs when MCAN calls mcan cls module provided by Ti.
Hi Rishabh, I have attached Screen shot for MCAN Interrupt enable register: Regards, Bikash
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Forum Post: RE: Linux/PROCESSOR-SDK-AM335X: Kernel boot hangs on custom board
Hi Kemal, Thanks for very quick response. We tried with both am335x-evm.dtb and am335x-evmsk.dtb. Still the same result. Regards Srinivasa
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Forum Post: RE: AM6546: Video encode performance
Hi Deep, Can you run the 'top' command and verify your encoder is running multi-threaded? AM65x does not have hardware video encode/ decode, so will become CPU-bound quite easily when running an encode operation. AM57x does have hardware encode/ decode accelerator (IVA-HD). More information is here: http://www.ti.com/processors/digital-signal-processors/libraries/am57x-video-codecs.html Regards, Mike
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Forum Post: RE: CCS/TMS320C6654: It doesn't seem that Main PLL configuration to be changed with gel or in my initialize function.
M_N_, I need some clarification. Were the attached GEL file and geloutput.txt collected from the EVM? The EVM has a REFCLK of 100MHz so using : #define PLL1_M 11 #define PLL1_D 0 will result in a core clock running at 600MHz as displayed in the output text. Have you looked at the SYSCLKOUT pin using a scope? You should see SYSCLK/6 or 100MHz in this case. Tom
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Forum Post: RTOS/AM5728: PCIe Root-complex registered ISR is not invoked when Endpoint raises interrupts
Part Number: AM5728 Tool/software: TI-RTOS Hello, We are working on a custom board carrying AM5728 SOM Module from Phytec with following setup, - Board carries Xilinx Artix-7 connected over PCIe bus (containing FPGA endpoint implementation) to the SOM module - ARM on AM5728 is used to load DSP firmware using remoteproc method - DSP firmware running SYS/BIOS enumerates the endpoint using the provided pcie libraries On the software front, - Linux 4.9.41 used is for booting is from Phytec GIT-repo ( stash.phytec.com/.../browse - The default device-tree has been updated to remove all entries related to PCIe (Root-complex, PCIe-phy, PCIe-endpoint, pcie clocks) along with Linux Bus support for PCI - This (pcie root-complex 1) is used by the DSP1 core for communication with endpoint implemented in FPGA - DSP application only registers MSI interrupt and handler (details below) with endpoint and profiles the received interrupts Following is the code snippet for registering ISR handler for IRQ_CROSSBAR_233 (PCIe_SS1 interrupt 1) as seen Table 17-13 (spruhz6k.pdf). -- void PCIE_setup_ISR(PCIE_EP_Handle ephandle) { Pcie_Handle handle = ephandle->handle ; HwiP_Params hwiInputParams, hwiInputParams0; HwiP_Handle pcieHwi; CSL_XbarIrqCpuId cpu; uint32_t cpuEvent; uint32_t xbarIndex; int32_t vector; pcieRet_e retVal; pcieRegisters_t regs; pcieRegisters_t epRegs; pcieTiConfIrqStatusMsiReg_t rcMsiStat; pcieTiConfIrqEnableSetMsiReg_t rcMsiEn; pciePlconfMsiCtrlAddressReg_t rcMsiLowAddress; pciePlconfMsiCtrlUpperAddressReg_t rcMsiUpAddress; pciePlconfMsiCtrlIntEnableReg_t rcMsiIntEnable; pciePlconfMsiCtrlIntStatusReg_t rcMsiBits[8]; pcieMsiCapReg_t epMsiCap; pcieMsiLo32Reg_t epMsiLowAddress; pcieMsiUp32Reg_t epMsiUpAddress; pcieMsiDataReg_t epMsiDataVal; int32_t i; memset (®s, 0, sizeof(regs)); memset (&epRegs, 0, sizeof(epRegs)); memset (&rcMsiEn, 0, sizeof(rcMsiEn)); memset (&rcMsiLowAddress, 0, sizeof(rcMsiLowAddress)); memset (&rcMsiStat, 0, sizeof(rcMsiStat)); memset (&rcMsiUpAddress, 0, sizeof(rcMsiUpAddress)); memset (&rcMsiIntEnable, 0, sizeof(rcMsiIntEnable)); memset (&epMsiCap, 0, sizeof(epMsiCap)); memset (&epMsiLowAddress, 0, sizeof(epMsiLowAddress)); memset (&epMsiUpAddress, 0, sizeof(epMsiUpAddress)); memset (&epMsiDataVal, 0, sizeof(epMsiDataVal)); /* Read existing EP registers */ epRegs.msiCap = &epMsiCap; epRegs.msiLo32 = &epMsiLowAddress; epRegs.msiUp32 = &epMsiUpAddress; epRegs.msiData = &epMsiDataVal; retVal = Pcie_readRegs (handle, pcie_LOCATION_REMOTE, &epRegs); if (retVal != pcie_RET_OK) { Log0("read of EP interrupt regs failed"); exit(1); } /* Enable MSI on EP */ epMsiCap.msiEn = 1; epMsiCap.multMsgEn = 0x4 ; epMsiDataVal.data = PCIE_WINDOW_MSI_DATA; epMsiUpAddress.addr = 0; epMsiLowAddress.addr = PCIE_WINDOW_MSI_ADDR>>2; /* because lld wants upper 30 bits only */ retVal = Pcie_writeRegs (handle, pcie_LOCATION_REMOTE, &epRegs); if (retVal != pcie_RET_OK) { Log1("write of EP interrupt regs failed (%d)\n", retVal); exit(1); } /* Clear any pending interrupts inside PCIE */ regs.tiConfIrqStatusMsi = &rcMsiStat; rcMsiStat.inta = rcMsiStat.intb = rcMsiStat.intc = rcMsiStat.intd = 1; rcMsiStat.msi = 1; /* Clear any MSIs */ for (i = 0; i pcieHwi = HwiP_create( vector , PCIE_EP_Isr, &hwiInputParams); if (! ephandle->pcieHwi) { Log0("Hwi create failed"); } } -- xbarIndex is using value 17 as picked from ( http://www.ti.com/lit/ug/sprugw0c/sprugw0c.pdf ) Table 9-2 vector is using 12 with usable range as mentioned in section 9.1.2 (Twelve maskable hardware interrupts from INT4 through INT15) CSL_XBAR_PCIe_SS1_IRQ_INT1 with value of 233 as defined in csl_device_xbar.h in pdk In the CCS SYS/BIOS cfg file following lines are present related to PCIe, -- var socType = "am572x"; var Pcie = xdc.loadPackage('ti.drv.pcie'); /* Enable only if soc-specific library should be used */ Pcie.Settings.socType = socType; -- Problems/Questions I have, 1. Above ISR setup is called after complete enumeration of Endpoint is done. I do not see the registered handler (PCIE_EP_Isr) getting invoked. But if we enable the PCIe bus support on Linux along with all PCIe DTS entries for RC, Phy, clock, etc, I see the registered ISR handler on DSP getting invoked (not sure how or why). I only want DSP to be receiving the interrupts from PCIe-endpoint and Linux to be completely disabled/cutout from accessing PCIe. Am I missing anything during initialization? 2. If Root-complex is enabled from both Linux/ARM and RTOS/DSP, then DSP is missing some interrupts (endpoint raises interrupts once every 1ms). But enabling PCIe-RC driver from both ARM and DSP may be the reason here and this brings me back to my first problem. Interrupts from Endpoint are definitely coming, but I am missing something during ISR registration on DSP side. 3. Should anything be enabled from Linux side for PCIe to work on DSP? 4. I do not completely understand the hardcoded value (31) as given in the sample examples. Some clarification on this will help What have I tried till now (with PCIe completely disabled from Linux), 1. Checked if interrupts are being seen on CSL_XBAR_PCIe_SS1_IRQ_INT0 (Crossbar 232) the Hwip_create itself fails here 2. Changed the event/vector values to 50/5, 49/11, but did not invoke the ISR handler 3. Ran with and without 'Pcie.Settings.socType = socType;' in cfg file with no difference in behavior Any inputs here will be helpful. thanks-- Somesh
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Forum Post: RE: CCS/TMS320C6654: It doesn't seem that Main PLL configuration to be changed with gel or in my initialize function.
M_N_, Also note that I do not believe that you are capturing and displaying the MAINPLLCTL0/1 registers correctly. See the attached XLS. The parsed values are not valid. The PLLD=0x28 and the PLLM=0x800 and the reserved values are wrong. Tom (Please visit the site to view this file)
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Forum Post: RE: Linux/PROCESSOR-SDK-AM335X: Kernel boot hangs on custom board
Can you enter this command in U-Boot console and retry? => setenv fdt_high 0x8c000000
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Forum Post: RE: CCS/AM5728: VIP example JTAG connect issue
Hi, We tested on the AM572x GP EVM (same as the X15 you used + LCD) and didn't see such loading issue. One possibility is that pdk_am57xx_1_0_11 is too old and had some issues, but it is unlikely. We recently tested on the latest pdk_am57xx_1_0_14, it also worked. It is unclear how you build the test example, " root/workspace_v7/vps_CaptureVipExample_evmAM572x_armExampleProject/Debug/vps_CaptureVipExample_evmAM572x_armExampleProject.out"=====> most likely you used CCS project. Please note that CCS projects are only available for IDKAM57x EVMs, not GPEVMs. What you built on IDK can't be run on GP. My suggestion: 1) move to latest 1.0.14 2) Please use "make vps" to build it to make sure it is working, you can load and run. 3) If you want to create CCS project for EVM, please follow http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#vps-drivers don't miss: -DBOARD=evmAM572x ====>This is most likely the cause you have load error. Regards, Eric
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Forum Post: RE: Linux/AM5728: GPMC doesn't work
1. I am wondering if you could please share more information on how you are connecting the GPMC. Please keep in mind that GPMC has to be configured as a host/master device and GPMC cannot be driven by other devices. 2. Are there any other devices driving the CS or any other pins in your configurations? -- This is confidential information So, I will share this Pin MUX and HW connection at via private message. 3. In your setup, please share how you are asserting the CS0? -According to previous .patch file, we defined CS0 base address to temporarily "0x01000000". So, when we embedded devmem command in busybox We defined # busybox devmem 0x01000000 0x00000000 If this setting is correct, we can get some data from connected device. However, it didn't see any Hardware signal and return "0" address at nearly address.
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