Andre, The functionality provided by GEL file in the debug environment of enabling clocks, and modules and setting up the external DDR memory is provided by the secondary bootloader software that we provide in the Processor SDK RTOS. The secondary bootloader is part of a two step boot process where the ROM bootloader on the device loads the secondary bootloader code to MSMC memory from flash or supported boot media and then the secondary bootloader (user defined) sets up the clocks, PSC and DDR memory and copies the application from an offset in flash to device memory. The secondary bootloader software and documentation is provided in PRocessor SDK RTOS and documented in the software developers guide: http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_Foundational_Components.html#k2h-k2e-k2l K2H device doesn`t support SDMMC interface or booting from it. We provide flash programming utilities that allow programming of flash over JTAG as you can see from the description. The .out that you are using in CCS needs to be converted to a app binary file using the utilities out2rprc.exe and MutlicoreImageGen.exe as described in the software developers guide. As far as porting K2H EVM to your custom design is concerned, you need to follow the process that is described here: http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#custom-board-addition Regards, Rahul
↧
Forum Post: RE: RTOS/66AK2H12: Moving from the GEL file on the EVM, to SoC initialization on production chip
↧
Forum Post: RE: TDA2E: TDA2E
Tomasz, Maybe I'm missing something … but if you're in 8b YUV mode shouldn't only vout2_d[7:0] be used? Can you tell me the MUXMODE register settings for all of the signals mapped to VOUT2_d[9:0]? Can you double check on a passing and failing scenario? Can you also give a snippet of the block diagram or schematic showing how the VOUT interface is connected? Thanks, Kyle
↧
↧
Forum Post: RE: TMS320C5535: SPI not working
Hi Khyati, Have you managed to make any progress with this issue? Looking at the code you attached, I would recommend writing to PSRCR before writing to PRCR (and writing to PCGCR before PSRCR). CSL_FINS(sysRegs->PRCR, SYS_PRCR_PG4_RST, CSL_SYS_PRCR_PG4_RST_RST);//1 CSL_FINS(sysRegs->PCGCR1, SYS_PCGCR1_SPICG, CSL_SYS_PCGCR1_SPICG_ACTIVE);//2 /* Value of 'Reset Counter' */ CSL_FINS(sysRegs->PSRCR, SYS_PSRCR_COUNT, 0x20); The Peripheral Software Reset Counter Register (PSRCR) specifies the number of cycles to assert peripheral reset. Writing to the Peripheral Reset Control Register (PRCR) (with a 1 in any bit field) initiates the peripheral reset for the number of cycle secified in PSRCR. By writing to PRCR before PSRCR, the reset time period might be 0 cycles, not effectively resetting the peripheral(s) being reset. Regards, Mark
↧
Forum Post: RE: CCS/AM5718: Problem while using pinmuxtool generated file
The AM572x pinmux data due to IODELAY configuration settings needs to execute from OCMC or any onchip memory. that code is in place to ensure that the code executes from onchip memory. Please make the update in linker command file or BIOS configuration as recommended here: http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_board.html#application-integration-for-am5x-dra7xx Please make the updates and let us know if this doesn`t resolve your issue. Regards, Rahul
↧
Forum Post: RE: PROCESSOR-SDK-OMAPL138: CSL update breaks project
Hello Rahul I'm sorry, but the so called documentation for CSL/GPIO is a joke! What do I expect form a documentation? First of all a function reference. Every function in the CSL and it's parameters should be listed and explained. Which headers do I need to include? Example code for a module such as GPIO should be as simple and minimal as possible. Nobody want's to read 500 lines of C code config files only to toggle an output pin. > Users are required to include top level CSL header for the module for example for GPIO include cslr_gpio.h and csl_gpio.h and then add a compiler define for the SOC being used -D SOC_OMAPL138. the macro definition defines the version of the IP included and pulls in the required APIs. OK. > 1. Setup the PINMUX for the SOC to configure the GPIO pin as input or output and configure the mux mode. OK. > 2. Enable the power to module using PSC OK > 3. Use CSL API to indicate pin and port number of the GPIO How do I do that? > 4. Setup the GPIO output using GPIOPinWrite_vX or GPIOPinRead_vX. where X is the version number of the IP on the SOC. OMAPL138/C6748 uses version v0. OK, so I would have to MANUALLY #include ? This is confusing. How could I know that OMAL138 is using V0 of GPIO? Why do I even have to care about the version? The project already KNOWS that I want to compile for OMAPL138, so why doesn't the CSL handle this automatically? > Your understanding of banck number and pin number is correct. The base address that you pass will provide the port number. But how in detail do I do that? The CSL only defines one baseAddr for GPIO: CSL_GPIO_0_REGS. There are no defines like CSL_GPIO_6_REGS and so on... Could you PLEASE simply provide a one line example for how to set pin GP6P15 to HIGH using GPIOPinWrite() ?
↧
↧
Forum Post: AM3354: watchdog during the ROM code (power-on booting)
Part Number: AM3354 1. the ROM code will configure Watchdog Timer 1 (set to three minutes) Did it mean that the watchdog would kick the processor to restart the boot sequence after 3 minutes if the power on boot-up was failed? 2. The watchdog can not be disabled by ROM code. What's the reason that the watchdog didn't kick the "reboot" sequence. was it because entering the SPL (or MLO) stage?
↧
Forum Post: RE: RTOS/TMS320C6748: Understanding SYSBIOS benchmarks
[quote user="Dean Hofstetter"] The benchmark "HWI dispatcher" should be renamed "Hardware Interrupt returning to same TASK". At any rate, here is how I think I need to proceed to measure my HWI load on the system. 1. If my HWI doesn't include SYSBIOS calls to post a SWI or post a Semaphore, then use the "HWI dispatcher" time. [/quote] Yes [quote user="Dean Hofstetter"] 2. If my HWI includes a SYSBIOS call to a post a SWI, then use "Hardware Interrupt to SWI interrupt" time. [/quote] Yes [quote user="Dean Hofstetter"] 3. If my HWI includes a SYSBIOS call to post a Semaphore, then use "Hardware Interrupt to blocked Task" time. [/quote] Yes [quote user="Dean Hofstetter"] Finally it doesn't say if the benchmark numbers provided are: min, max, or avg. I'm assuming avg. You would have to throw a few cycles onto all the numbers if you had a cache miss for each L1P or L1D (or both). [/quote] The are averaged. The benchloop example is included within kernel releases to show exactly how the benchmarks are collected.
↧
Forum Post: RE: 66AK2H14: How DDR3 memory controller manage write accesses ?
For the source file that contains the test code, please follow the directions in the article How to Submit a Compiler Test Case . That should allow me to comment on the performance difference between -o0 and -o3. However, I doubt I will be able to shed light on why the DDR3 memory interface acts differently. Thanks and regards, -George
↧
Forum Post: RE: Linux/AM5728: Switching between DHCP client and server
Hi, To be able to switch between client and server is most likely possible but it is beyond the scope of support from TI since this resides above the CPSW driver in the user space area that is manged by SystemD. The current SDKs start a SystemD service that initializes a udhcpc on boot in an attempt to get an IP address for the interface. This start up service would need to removed and a new SystemD service would need to be created that would manage the start of either a client or server based on user input. There maybe examples of how to do this in the SystemD community or found on the web. Best Regards, Schuyler
↧
↧
Forum Post: RE: AM5726: EtherCAT jumbo frame support
Hi Paula-san, Thank you for your support. [quote user="Paula Carrillo"]just want to confirm, you are communicating two AM5726 , one running as a master and one as slave. Is this correct? [/quote] Yes this is correct. [quote user="Paula Carrillo"]On the other hand, let me check with our developers if there is any limitation with Jumbo frames.[/quote] I'm looking forward to hearing from you.
↧
Forum Post: RE: CCS/TMS320C6678: ISR execute and receive data process in the hyplnk_exampleProject
Hi. It took some time to get around the activation of the interrupt, but it was resolved by referring to the data provided. I'll also look at the additional data. Thank you.
↧
Forum Post: Linux/AM6548: AM65xx IDK Gstreamer encoding with PowerVR GPU
Part Number: AM6548 Tool/software: Linux Hi All, I have a AM65xx IDK eval board that is streaming a webcam feed through TCP to a web browser on the same network. I am using gstreamer to grab the video and encode it before it is sent over the network. I was wondering how I can use the GPU to do the encoding part for me. If this is possible, how would i go about doing so. Thank you, Steven
↧
Forum Post: RTOS: TDA2xx Can't Set eth1 IP adress of ndk_nsp_hook.c
Tool/software: TI-RTOS I want to set IP adress of 2 ports of TDA2xx , My process is as follows (1)Set enableStaticIpEth0 and enableStaticIpEth1 value = 1 in NDK_config.cfg (2)Set eth0 IP adress in NDK_config.cfg (3)Set eth1 IP adress of function named stackInitHookStaticEth1 in ndk_nsp_hooks.c (4) compiler and update AppImage the result of (2) is work, and it can be shown on the serial console output, but (3)'s IP show "0.0.0.0", how to resolve this problem? thanks~
↧
↧
Forum Post: Linux/PRU-ICSS-INDUSTRIAL-SW: How can I create a driver that will be probed when a PRU starts, and removed when it stops?
Part Number: PRU-ICSS-INDUSTRIAL-SW Tool/software: Linux How can I create a driver that will be probed when a PRU starts, and removed when it stops? One thought was to have my PRU firmware create an unused RPMsg channel and have RPMsg probe my driver by giving it a matching name, like what is done with the rpmsg-client-sample driver, but then have my code just do its own thing. This seems like a kludge though.
↧
Forum Post: Linux/AM5728: openCV and openCL issue
Part Number: AM5728 Tool/software: Linux Hello! My program used opencv but I don't want to use the opencl and dsp. When I disabled the dsp in the devicetree, the program will not run properly on the evm. So, what should I do to run the app properly without the dsp?
↧
Forum Post: 66AK2G12: CHIP BEAD needed for TPS65911A GNDA_PMIC/GDNREF ?
Part Number: 66AK2G12 Hi, My customer is considering to use registers rather than chip beads on TPS65911A GNDA_PMIC/GDNREF. Please take a look at the EVM schematic : Our PMIC FAE is saying this is not specific requirements for TPS65911A . So I posted the questions here. Could you clarify the reason for using chip beads ? Best Regards, NK
↧
Forum Post: Linux/AM4376: About LPDDR2 autoinitialization issue
Part Number: AM4376 Tool/software: Linux Hi SIr We used LPDDR2 (EDB8132B4PB) for AM4376 and would like to optimize DDR timing by using CCS. We found the CCS is waiting for LPDDR2 autoinitialization for a long time and cannot finish successfully GEL modification //========================================================================// //******************************************************************************** //******************************************************************************** // LPDDR2 Initialization //******************************************************************************** //******************************************************************************** #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 //no pullup/down on addr/ctrl #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 //no pullup/down on addr/ctrl #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x00000294 //Slew rate: fast, Impedance: 44ohms, no pullup/down #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS //timings for 266MHz LPDDR2 (8Gb) #define LPDDR2_PHY_CTRL 0x0E288006 //0x0E284006 //for 266MHz LPDDR2 #define LPDDR2_SDRAM_TIMING1 0xEA86B411 //0xEA86B411 #define LPDDR2_SDRAM_TIMING2 0x103A0E8A //0x103A0E8A #define LPDDR2_SDRAM_TIMING3 0x5F6BA37F //0x0F6BA37F //#define LPDDR2_SDRAM_CONFIG 0x808052BA //16-bit LPDDR2 #define LPDDR2_SDRAM_CONFIG 0x808012B3 #define LPDDR2_REF_CTRL 0x0000040D //266 * 3.9us = 0x40d #define LPDDR2_ZQ_CONFIG 0x5007FA67 //0x50074BE4 //========================================================================// (Please visit the site to view this file) please advise.
↧
↧
Forum Post: Linux/AM5728: Registers about ARM Coresight PTM
Part Number: AM5728 Tool/software: Linux Hi I am using AM5728 evaluation board and testing ARM Coresight PTM. I found some registers about PTM(like MPU_C0_CS_PTM_MPU) in AM572x Sitara Processor Technical Reference Manual, but there is no description about them so it is hard to utilize. I need information of registers about PTM, ETB, TPIU, FUNNEL etc.. but hard to find. Is there somebody can help me? Thanks
↧
Forum Post: DRA80M: SDIO Configuration for eMMC
Part Number: DRA80M I am using MMC0 to interface with an eMMC @ 3.3V. I am not using MMC1. I currently have VDDS7 being supplied by CAP_VDDA_1P8_IOLDO0 and VDDS6 being supplied by CAP_VDDA_1P8_SDIO. (1) Should I be using the SDIO LDO when using eMMC or is it only intended for an SD Card? (2) Do I configure MCU_BOOTMODE_09 as '0' (MMC0) even though I am operating the I/O @ 3.3V? (3) If the answer is to not use the SDIO LDO (change VDDS6 to CAP_VDDA_1P8_IOLDO1) - how should MCU_BOOTMODE_09 be configured?
↧
Forum Post: WEBENCH® Tools/AM3352: NAND Flash programming tool
Part Number: AM3352 Tool/software: WEBENCH® Design Tools I have one another query. I am exposing AM335X_StarterWare_02_00_01_01 API but in that using available API I am trying to store ECC data into NAND Flash Spare region but I unable to store data into that region. If you have sample c code to store data into NAND Flash spare region please share it.
↧