Part Number: AM5726 Hi everyone, When I implement Ethercat Master and Slave with AM5726 , can I communicate with jumbo frames respectively? If communication is possible with jumbo frames, what is the byte size of the frame? Best regards, Sasaki
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Forum Post: AM5726: EtherCAT jumbo frame support
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Forum Post: TDA3MV: FMEDA
Part Number: TDA3MV We need for the above mentioned device a detailed FMEDA to import these results into our product FMEDA. Is a FMEDA in EXCEL readable Formate available? Do you have allocation of chip area (may be in percentage) to the function of the device? Thank you for your support. Best regards Viktor Tiederle
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Forum Post: TMDSEVM572X: How to access GIPO in this AM572X EVM kit
Part Number: TMDSEVM572X Hi, how to access the GIPO in this AM572x EVM kit? If any connector may i buy to access GPIO on this board?
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Forum Post: Linux/AM5718: about VIP function of AM5718 with PROCESSOR-SDK-LINUX-RT-AM57X 05_02_00_10
Part Number: AM5718 Tool/software: Linux Hello, TI Experts, Our customer sent us questions about VIP function of AM5718 below condition. - PROCESSOR-SDK-LINUX-RT-AM57X 05_02_00_10 - EVM: TMDXIDK5718 They tried to connect "12bit gray scale sensor" to vin1a and vin2a. And they would like to know how to modify the related files in Linux-RT-SDK. They also checked the description of "9.4.4.3 VIP Slice Processing Path Examples" in the below TRM. http://www.ti.com/lit/ug/spruhz7i/spruhz7i.pdf But they cannot find any description for "12bit gray scale sensor" use-case. Questions: 1:Could you tell us the recommended configuration values including like below setting to use "12bit gray scale sensor"? VIPx_CSC_SRC_SELECT = VIPx_SC_SRC_SELECT = VIPx_CHR_DS_1_SRC_SELECT = VIPx_CHR_DS_1_BYPASS = VIPx_CHR_DS_2_SRC_SELECT = VIPx_CHR_DS_2_BYPASS = VIPx_RGB_SRC_SELECT = VIPx_RGB_OUT_HI_SELECT = VIPx_RGB_OUT_LO_SELECT = VIPx_MULTI_CHANNEL_SELECT = 2: Those register settings are same as vin1a and vin2a. Is this understanding correct? 3: They thought that the VIP setting is in "drivers/media/platform/ti-vpe/vip.c". Is this understanding correct? 4: Are there any recommended modification files to use "12bit gray scale sensor" in Linux-RT-SDK other than vip.c? 5: Are there recommended way to realize to marge vin1a and vin2a data into one picture by using such as "9.4.8.7.1.1.6 Line Stride in TRM" function like below? - Left half image is vin1a 12bit gray scale data. - Right half image is vin2a 12bit gray scale data. (Please refer attached pdf.) We would also appreciate if you tell us the recommended way of realizing to marge" vin1a and vin2a 12bit gray scale data" into one picture. Best regards, (Please visit the site to view this file)
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Forum Post: Linux/PROCESSOR-SDK-AM335X: [armv7 A8 TI am335x] Illegal Instruction
Part Number: PROCESSOR-SDK-AM335X Tool/software: Linux Part Number: TI am335x SITARA Here is the description of the problem (C code presented): #include static void asm_read_attr_reg4(void) { unsigned int reg_value; printf("Start\n"); __asm ("mrc p15, 0, %0, c0, c2, 4" : "=r"(reg_value) ); printf("Instruction Set Attributes Register 4: 0x%08x\n", reg_value); if (0x000f0000 & reg_value) { printf("The processor does support DMB, DSB and ISB instructions\n"); } else { printf("The processor does NOT support DMB, DSB and ISB instructions\n"); return; } return; } void main(void) { asm_read_attr_reg4(); } Here are the compilation options and execution of this code: root@beaglebone:~/projects/LKM/cp15_smc# gcc --machine=arm -march=armv7-a+fp -mfpu=vfp -mfloat-abi=hard test.c -o test root@beaglebone:~/projects/LKM/cp15_smc# ./test Start Illegal instruction root@beaglebone:~/projects/LKM/cp15_smc# Why the __asm ("mrc p15, 0, %0, c0, c2, 4" : "=r"(reg_value) ); is after all Illegal Instruction??? Thank you, _nobody_
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Forum Post: CCS/TMDX654IDKEVM: PRU LED blink example
Part Number: TMDX654IDKEVM Tool/software: Code Composer Studio Hello, I am trying to blink LED on my IDK . I have created CCS project for PRU of AM65x IDK as mentioned here , LAB1 http://processors.wiki.ti.com/index.php/PRU_Training:_Hands-on_Labs#LAB_1:_Toggle_LED_with_PRU_GPO . Here is main.c : #include // for uint32_t volatile register uint32_t __R30; int main(void) { uint32_t gpo; while (1) { gpo = __R30; gpo ^= 0xFFFF; __R30 = gpo; // 10 to the 8th == half-second delay __delay_cycles(100000000); } } From "debug" button drop down I selected my project and connected to PRU0 ,it started debug session but no LED is blinking after running a program. Is my program correct ? anything missing . Please help. Also , How can I debug other projects from pru-software-support-package ? any leads appreciated
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Forum Post: PROCESSOR-SDK-AM335X: i2c example code
Part Number: PROCESSOR-SDK-AM335X Hi, I am using I2C_skAM335x example project but in debugging mode nothing is coming to terminal. I am not getting whether i2c is working or not. Regards Gaurav
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Forum Post: AM1808: Repair and move blocks with bitflips
Part Number: AM1808 We have some problems/questions regarding the scrubbing procedure in the AM1808 using UBIFS. We use 4 bit ECC. In the scrubbing procedure, we read the full UBIFS partition and we observed that in case of a bitflip error, the whole block is repaired and moved to another location. However, we have encountered some situation that we do not understand. Your help is very much appreciated. 1 Questions: 1) What is the meaning of “Error_address > 512“? (Ref. davinci_nand.c)? We have observed that the error_address in davinci_nand.c was greater than 512 with the result that the related block was not repaired. What is the meaning of NAND_ERR_ADD1/2_OFFSET and NAND_ERRVAL1/2_OFFSET (NANDERRADD1/2, NANDERRVAL1/2 register, see references) ? Under which conditions can this value be greater or equal than 512? 2) What are the limitations of the scrubbing procedure? According to our understanding it is guaranteed to correct at least 4 bitflips. As the number of bitflips increases over time, we need to ensure that a block gets repaired and moved before it reaches the 4 bitflips limit. We observed that under certain situations a bitflip is not repaired by the scrubbing procedure (ref. Question 1). Can there be situations that the number of bitflips reaches the 4 bit limit and the block does not get repaired/moved? 2 References PROCESSOR : root@am1808-evm:~# cat /proc/cpuinfo Processor : ARM926EJ-S rev 5 (v5l) BogoMIPS : 149.50 Features : swp half thumb fastmult edsp java CPU implementer : 0x41 CPU architecture: 5TEJ CPU variant : 0x0 CPU part : 0x926 CPU revision : 5 Hardware : AM1808 EVM Revision : 0000 Serial : 0000000000000000 KERNEL : root@am1808-evm:~# uname -a Linux am1808-evm 2.6.37-1.97.0-r22504 #1 PREEMPT Tue Mar 26 02:23:30 CET 2019 armv5tejl GNU/Linux spruh82b AM1808 tech ref manual 2016-07.pdf, chapter 19.4 D0h NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 1 Section 19.4.20 D4h NANDERRADD2 NAND Flash 4-Bit ECC Error Address Register 2 Section 19.4.21 D8h NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1 Section 19.4.22 DCh NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2 Section 19.4.23 davinci_nand.c The relevant code section is here: /* Correct up to 4 bits in data we just read, using state left in the * hardware plus the ecc_code computed when it was first written. */ static int nand_davinci_correct_4bit(struct mtd_info *mtd, u_char *data, u_char *ecc_code, u_char *null) { ... correct: /* correct each error */ for (i = 0, corrected = 0; i 1) { error_address = davinci_nand_readl(info, NAND_ERR_ADD2_OFFSET); error_value = davinci_nand_readl(info, NAND_ERR_ERRVAL2_OFFSET); } else { error_address = davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); error_value = davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); } if (i & 1) { error_address >>= 16; error_value >>= 16; } error_address &= 0x3ff; error_address = (512 + 7) - error_address; if (error_address < 512) { data[error_address] ^= error_value; corrected++; } } return corrected; }
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Forum Post: RTOS/AM5728: SMP execution hangs
Part Number: AM5728 Tool/software: TI-RTOS Hi, I tried to modify our application to use SMP on the AM5728 Rev1.3B. I followed the instructions. processors.wiki.ti.com/.../BIOS processors.wiki.ti.com/.../Public_SmpBiosSlides.pdf software-dl.ti.com/.../ccs_smp-debug.html But the execution hangs up at: ti_ sysbios _family_arm_a15_smp_Core_resetOMAP5xxx_I() According to the instructions in this case, I should wake up the second core through a gel script. But I didn't find any hint how to do this. Is there an example? Thanks & Best regards Daniel
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Forum Post: Linux/AM3358: Delay between SPI CS and clock
Part Number: AM3358 Tool/software: Linux Hi there I want to send some data to a micro controller with a beaglebone black (beagle bone is master). As shown in the picture, the delay between falling edge of cs and first rising edge of clock is too much. could you please tell me how to decrease it? the image is taken from a logic analyzer which its sampling rate is lower than SPI bitrate. thanks a lot.
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Forum Post: Linux/TDA2SX: Failed to debug spl/u-boot-spl, it stoped in cpu_init_cp15
Part Number: TDA2SX Tool/software: Linux Dear TI, I am now try to review spl code follow debug probe to confirm some questions. But every time i try to add hardware breakpoint at funtion entry board_init_f. It cannot stop there. So i try to debug the code step by step. Finally i found that the exactlly position is in the file arch/arm/cpu/armv7/start.S: I have tried both step in or step over line 205 'v7_arch_cp15_set_l2aux_ctrl'. And then CCS reply me nothing. The resume button in the toolbar grey out. Then i can do nothing.... The CCS context looks like: After that, the registers probably changed to unable to read. I used vsdk version 3.6 and the corresponding uboot 2016.05 release. Before compiling the spl image, I added '#define DEBUG' in dra7xx_evm.h as: The u-boot-spl.bin used for debug can load uboot correctly in the normal startup senquence. My quetions: 1. Is it needed to and macro DEBUG shown above to debug the spl or u-boot? 2. How to solve the stoped in cpu_init_cp15 problem? 3. I got no flash devices with valid image to start the SoC when debugging, is that right? 4. I succeed to step over the cpu_init_cp15 function only once in the 4 hours debugging work.I don't know why. There is no difference to the other times when i failed here. The console output: Regards, Liu Gan
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Forum Post: TMS320C6746: mcasp StaterWare problem - undefined symbol
Part Number: TMS320C6746 Hi team, Right now, I'm working with TMS320C6746 and the TMDSLCDK6748 board. I installed CCS and StarterWare and am trying to work with the mcasp example as a starting point, so I created a new project based on it. I set up the project to use the StarterWare include directories, and for the libraries, I just copied drivers.lib and system_config.lib into the project directory and included them via the linker options.The trouble is I’m not finding a few symbols: undefined first referenced symbol in file --------- ---------------- EDMAVersionGet ../drivers_debug.lib I2CPinMuxSetup ./mcaspPlayBk.obj McASPPinMuxSetup ./mcaspPlayBk.obj Do you know how I can resolve these dependencies? Also, when I get something that does compile and link, then try to run it, I get: C674X_0: Trouble Writing Memory Block at 0x80000000 on Page 0 of Length 0x6c80: This operation is not supported by this driver C674X_0: File Loader: Verification failed: Target failed to write 0x80000000 C674X_0: GEL: File: C:\tmp\ti\workspace_v9\thumper_test\Debug\thumper_test.out: Load failed. I’m using the UART cable that came with the kit, and an unmodified C6748.cmd. Any ideas? Thanks, Brian
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Forum Post: RTOS/TMS320C5515: Function to call for establishing if DSP/BIOS Kernel is executing or not ?
Part Number: TMS320C5515 Tool/software: TI-RTOS Hi, I have a few I2C and SPI peripherals on the system board and these have various read, write, and configuration functions to initialize them. These functions may be called in main() or they may be called once DSP/BIOS is executing. I was wondering if there is a particular function to call or a register to poll to obtain status of the kernel, if it's actually executing or not. I'd like to adapt certain functions so they call TSK_sleep() when the kernel is running, otherwise to use a simple do-while(){} delay loop if being executed from the main(). For this to be possible I'd need to establish if the DSP/BIOS kernel is running or not. Would appreciate some advice of a way to do this. Regards, Michael
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Forum Post: TDA2PSX-ACD: Functional Safety FMEDA
Part Number: TDA2PSX-ACD We use the above mentioned part for our system. We had performed a FMEDA for our product and need to look more closely to the TDA2PSX-ACD . - Could you provide detail data for failure rate calculation? - Do you have an allocation of areas used for different sub-modules? - When switching to the device TDA2PHG-ACD is there anything we have to take into account from functional safety point of view? Thank you for your support. Best regards Viktor Tiederle
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Forum Post: RE: Linux/AM5718: Changing serial console
Hello Arpita, Can you make SPEEDSELECT = 20 MHz in your CTRL_CORE_BOOTSTRAP and check whether your board starts to boot? Best regards, Kemal
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Forum Post: RE: OMAP-L138: looking for early boot phase debugging hints
Hi Brad, thank you for this first hint, trying to connect via JTAG. ... please see my following two messages regarding my investigations to further isolate the problem. This question here only in order to remove the "TI thinks this solves the problem" status flag. Horst
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Forum Post: RE: RTOS/AM5728: VPS loopback example issue
Hi, I thought the code has a bug running on IPU core, but it should work on A15 or C66x, did you try those cores or your goal is to run on IPU? Regards, Eric
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Forum Post: RE: PROCESSOR-SDK-AM335X: SPI and I2C
[quote user="Gaurav Aggarwal1"] I am using PSDK TI-RTOS and skAM335x board. If I use ti\pdk_am335x_1_0_14\packages\MyExampleProjects\I2C_Example_skAM335x_armExampleProject then is will it affect the data of first 64 bytes of ID memory (EEPROM)? If I change #define I2C_EEPROM_TEST_ADDR 0x0001 to #define I2C_EEPROM_TEST_ADDR 0x80 in C:\ti\pdk_am335x_1_0_14\packages\ti\drv\i2c\test\eeprom_read\src\I2C_board.h. Will it affect first 64 bytes of EEPROM? [/quote] From what I understand, this example does not modify EEPROM ID memory. The example only reads 10 bytes from EEPROM memory and stores these 10 bytes in rxBuf[ ] array. txBuf[ ] array is used only to send high address byte (txBuf[0] = 0x0) and low address byte (txBuf[1] = 0x1). Regards, Pavel
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Forum Post: RE: RTOS/AM5728: SMP execution hangs
Hi, There is an existing SMP example on AM572x: This is part of TI Processor SDK RTOS release. Regards, Eric
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Forum Post: RE: Linux/TMDSICE3359: Boot time optimization
In 1.2.2.2. Build Steps: the command: ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-05.01.00.11-config.txt create the directory: tisdk/sources/meta-processor-sdk the shows an errors: error: inflate: data stream error (incorrect header check) error: File ad1d9c52ff7210ca2df9b57f2183ea9c7934685e ( arago-project.org/.../1d9c52ff7210ca2df9b57f2183ea9c7934685e) corrupt error: Unable to find ad1d9c52ff7210ca2df9b57f2183ea9c7934685e under arago-project.org/.../meta-processor-sdk.git Cannot obtain needed tree ad1d9c52ff7210ca2df9b57f2183ea9c7934685e while processing commit e9c4216f6407e86bd04ad7b544dbebde346e6135. error: fetch failed. ERROR: Could not clone repository at arago-project.org/.../meta-processor-sdk.git and delete the directory tisdk/sources/meta-processor-sdk. I. e., error on the lost of file in http://arago-project.org/git.
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