Part Number: 66AK2H14 Hi! I red in the DDR3 documentation, there is a notion of "open" bank. What it means ? When a bank is closed ? An open bank could be closed ? Does it takes time to open a bank ? Best Regards, François
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Forum Post: 66AK2H14: What "open" banks means ? (DDR3 memory controller)
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Forum Post: AM3357: Does TI have PRU demo to do Δ-Σ modulator?
Part Number: AM3357 Hi all, Customer want to use PRU to do Δ-Σ modulator for AMC1305 decode. Does TI have similar demo for this? thanks! BR, Denny
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Forum Post: RTOS/AM5746: SMP task priority using MailboxPost
Part Number: AM5746 Tool/software: TI-RTOS Hi, I have a related question. In the previous question, priority operations are performed on the Running task of Core 1 directly from the Hwi interrupt. As another pattern, perform MailboxPost on Core0's highest priority task from Hwi interrupt, we want to do the priority operation of the Running task of Core1 from that task. Priority operations will deadlock as well as related question. Supplement: The reason for this control can be seen from the following E2E. Hwi → High Priority Core0 Task → Running Core1 Task e2e.ti.com/.../2792658 Question: Would you tell me the workaround and cause? Environment: pdk_am57xx_1_0_11 bios_6_76_00_08
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Forum Post: Linux/AM5728: Timezone change
Part Number: AM5728 Tool/software: Linux I want to change the system time by ntp but the system timezone is wrong. And I didn't find /etc/timezone in the filesystem. Where is it? Or there is other file which need to be change?
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Forum Post: PROCESSOR-SDK-AM335X: i2c example project
Part Number: PROCESSOR-SDK-AM335X Hi, I am using PSDK TI-RTOS and skAM335x board. If I use ti\pdk_am335x_1_0_14\packages\MyExampleProjects\I2C_Example_skAM335x_armExampleProject then is will it affect the data of first 64 bytes of ID memory (EEPROM)? Regards Gaurav
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Forum Post: RE: CCS/TMS320VC5509A: how to read sine wave (any frequency) signal by using MCBSP interface with Codec(HD44233)
Hi Muneeswaran, As I'm seeing the data sequence you have successfully ready from McBSP now you need to decode FSK modulated sin and detect caller ID. Unfortunately I can not suggest you a complete solution but you can take a look at a document describeing implementation of Caller ID software developed by SPIRIT Corp for TMS320C5400 platform at: Also you can search in the net for some open source FSK decoding / demodulating solutions. Hera are two examples: Regards, Tsvetolin Shulev
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Forum Post: RE: Linux/TMDXIDK5718: PCIe EP not recognized on Linux PC
Hi, Jason, where did you issue the lspci command, on the RC or EP? "lspci" command only works on RC. Rex
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Forum Post: RE: Linux/TMDXIDK5718: PCIe EP not recognized on Linux PC
Besides, the EP needs to come up first before RC as the PCIe EP user's guide indicates. Please search on E2E forum. There are several similar issues that the RC needs to rescan for EP.
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Forum Post: RE: CCS/TMS320VC5509A: how to read sine wave (any frequency) signal by using MCBSP interface with Codec(HD44233)
Thanks for your support
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Forum Post: RE: I want to ask if TMDXEVM6657LE contains XDS560v2 USB JTAG or I need to by this additonal
Hi, It seems that they have XDS200 onboard emulator: Best Regards, Yordan
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Forum Post: RE: RTOS/TMS320C6678: Implement rtiostream protocol for data exchange via tcp
Hi, Which Processor SDK RTOS & NDK versions are you using? Best Regards, Yordan
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Forum Post: RTOS/TMS320C6655: RTOS/TMS320C6655
Part Number: TMS320C6655 Tool/software: TI-RTOS Hi, I'm currently working on a board development for an avionic system and probably I need to get DO-178 certification DAL C. I'm going to use a TI TMS320C6655 or TI TMS320C6657 DSP for our project but there is no evidence about TI-RTOS certificability. Currently our TI-RTOS version is 6.42.03.35 . I would like to get at least a copy of the TI-RTOS Kernel Test suites and overview and documentation (if they can be forwarded) please. Thanks in advance for the availability. Best Regard, Carmine
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Forum Post: RE: SMV320C6727B-SP: Is 15 mV of ripple on pin PLLHV acceptable?
Will, I was not able to find any qualitative numbers for the allowed noise on PLLHV. However, subjectively 15mV of noise seems very reasonable from my experience. Regards, Wade
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Forum Post: RE: TDA2EVM5777: Issues building Processor Sdk Visual
Hi Aleksander, Glad that your issue is resolved. Very few customers have faced build issue due to installation. However a large number of customers including TI itself have never faced this issue. In case you can provide any insights to what went wrong first time it will be very useful. Regards, Rishabh
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Forum Post: AM5746: Detect PCIe Disconnection
Part Number: AM5746 Hi, We need your help. AM5746 (Root Complex) is placed on the main board and communicates with other board (End Point) via PCIe. There is possibility of this boards (EP) may be ejected without power off . In this situation, if AM5746 (RC) accessed PCIe outbound region during disconnecting link partner board, AM5746 would hang. Could you give us any idea to prevent this hang up ? Is it possible to detect this error without hang up? Or is it possible to recover from hang up ? We got some comments from the thread on E2E below.. https://e2e.ti.com/support/processors/f/791/t/802152 There are many PCIE error status registers, but I am not aware any of them is dedicated to detect PCIE disconnected. The disconnection caused the link down, you may look at the PCIECTRL_TI_CONF_DEVICE_CMD, bit 1:5 LTSSM_STATE for this purpose. However, the board (EP) may be ejected within very small window between checking LTSSM_STATE and starting to access PCIe outbound region. Also, it is difficult to check LTSSM state always or every access. AM57x has HPC (Hot-Plug Capable) and HPS (Hot-Plug Surprise) bit in PCIECTRL_RC_DBICS_SLOT_CAP register and HPI_EN (Hot-Plug Interrupt Enable) bit in PCIECTRL_RC_DBICS_SLOT_CAS register. Can we use these bit to detect PCIe disconnection ? Does any interrupt occur ? Best regards, Hideaki
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Forum Post: RE: CCS/TDA2P-ABZ: Automating NOR flashing: how to enable all cores
Hi Rishabh, I have made the changes I had mentioned in device.c and device.h and the built it to generate a new binary. When I load this binary using "Load Program" in CCS, I get an Abort as you can see from the screenshot below: Did I make an error in interpreting this line #define MODE(x) ((UInt32) 0x1 << ((x) - (UInt32) 1)) ? Should it be MODE(14) or MODE(16) if I want to give it write permission? Thanks in advance for your help in solving this issue. -Varsha
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Forum Post: RE: Linux/DRA80XMEVM: TFTP boot issue
Hello and thank you for your post. I think you are missing the commands to properly set your kernel command line. Can you try to run add the below command to your sequence: run args_mmc before you execute the booti instruction? The error means your kernel can't find a filesystem to start. This is passed on the kernel command line to Linux. I hope this helps.
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Forum Post: RE: CCS/TDA2P-ABZ: Automating NOR flashing: how to enable all cores
Hi Rishabh, The image did not get inserted in my previous message so here it is Thanks, Varsha
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Forum Post: RE: 66AK2H14: What "open" banks means ? (DDR3 memory controller)
Thanks for your answer, I understand better. Now I have another question, that I asked in another topic : e2e.ti.com/.../810423 If I sum up the test I am doing, I am writing data in DDR3A, and I look into DDR3 memory controller read and write accesses through performance counters. I have something unexpected in optimized and non-optimized code. Results in non-optimized code: Size (Bytes) Total Activates Read Write 4 1 1 2 1 8 2 1 2 2 16 4 1 2 4 32 8 1 2 8 64 16 1 2 16 128 32 1 2 32 256 64 1 2 64 512 128 1 2 128 1024 256 1 2 256 2048 512 1 2 512 4096 1024 1 2 1024 8192 2048 4 2 2048 16384 4096 12 2 4096 32768 8192 28 2 8191 65536 16384 61 2 16384 131072 32758 126 2 32767 262144 65536 256 2 65531 524288 123166 484 2 123172 1048576 254249 1001 2 254256 Result in optimized code: Size (Bytes) Total Activate Read Write 4 1 1 1 1 8 2 1 1 2 16 4 1 1 4 32 7 1 1 8 64 15 1 1 16 128 24 1 1 25 256 34 1 1 35 512 53 1 1 54 1024 71 1 1 72 2048 107 1 1 108 4096 178 1 1 179 8192 320 2 1 321 16384 605 4 1 605 32768 1174 8 1 1174 65536 2311 16 1 2312 131072 4587 32 1 4583 262144 9138 64 1 9139 524288 17256 123 1 17291 1048576 35457 254 1 35452 In my configuration I have 65536 rows, 8 banks, 1024 word (of 32-bit) per page, I use only 1 chip select, the data bus width is 32-bit, and I write data of 32-bit. I have therefore, some unexpected results in terms of accesses. First of all: In optimized code : I have only 35452 write accesses for 1048576 bytes written, that means there are write accesses of 29 bytes. In non-optimized code: there are 25426 writes of 4 bytes (1048576 bytes) --> OK Secondly: - In optimized code for instance: I had 1 activate for 4096 bytes written (OK, that is the size of a page), 8192, 2 activates (OK), ... - In non-optimized code in the same example: there is 1 activate for 4096 bytes written (OK) but 4 activates for 8192 bytes (I expected 2). Do I need to create a new topic on this point ? or continue in the topic I linked here ? Do you need other information ? Do you have an idea for to explained my results ? Best Regards, François
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Forum Post: RE: Linux/EVMK2H: EDMA3 Testing
Hi, j e, All 5 of the EDMA3 CC are not enabled in K2H release. Please refer to K2G DTS file, keystone-k2g.dtsi, on how to enable them. We don't have example of using EDMA on K2H and the User Space application is not in TI support scope. I know PCIe EP test on other device uses EDMA which may give you some idea, but again, that is on different device, AM5728 , and in the PLSDK for that device. The code is in linux/drivers/misc/pci_endpoint_test.c. Rex
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