Hi Delio, [quote userid="47253" url="~/support/processors-group/processors/f/processors-forum/1493646/processor-sdk-j722s-porting-freertos-mcasp-driver-from-asdk-10-00-00-for-am62dx-to-j722s"] Question 2: Line 61 of mcasp_soc.h from am62dx's asdk-10.00.00 contains the following #define /* CLEC offset for MCASP Interrupts */ #define MCASP_IRQ_CLEC_OFFSET (256U) Does the DSP on j722s use the same constant value or does it need different one? I cannot fine this information anywhere in the TRM or source code I looked at. [/quote] Can you test with using 192U and let me know your results? [quote userid="47253" url="~/support/processors-group/processors/f/processors-forum/1493646/processor-sdk-j722s-porting-freertos-mcasp-driver-from-asdk-10-00-00-for-am62dx-to-j722s"] Question 3: in the mcasp_{SOC}.syscfg,js metadata file what is the correct value for the c7xRxIntr and c7xTxIntr fields for MCASP 0, 1 and 2? I was able to find the the TX/RX event IDs in the TRM but not the interrupt numbers. [/quote] I am still looking into this, sorry for the delay. Thanks, Neehar
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