Forum Post: RE: question about scalar framerate
If I just invoke System_linkControl(encId, ENC_LINK_CMD_SET_CODEC_FPS, &encTargetFps, sizeof(encTargetFps)I can change the targetFrameRate,Enter Choice: [m3video] [m3video] *** ENCODE Statistics...
View ArticleForum Post: RE: DM369 upgrade from DM368
So is there any benefit to the DM369 if you are not using the noise filter?
View ArticleForum Post: RE: Problem when I using SPI and UART simultaneously on the...
This is fixed in latest CSL. A flag, PG4_flag, is set to ensure reset is performed only once in csl_sysctrl.c.Regards.
View ArticleForum Post: RE: Power dissipation
Aravind,The C6454 has a power consumption App Note and Spreadsheet at: http://www.ti.com/litv/pdf/spraae8b and http://www.ti.com/litv/zip/spraae8b. All power consumed must be dissipated as heat. The...
View ArticleForum Post: RE: The issue about DM368 with Sony ITN2 platform video output
Yes, the VD interrupt timing may need adjustment if you use IPNC RDK S/W.Your ISIF VDINT0/1/2 are set to 0x2c0 (704) which is for 720P in RDK (not 1080P).
View ArticleForum Post: RE: Endpoint-to-Endpoint communications using PCIe switch
there are some helps?
View ArticleForum Post: Parallelize a FFT on C6678
Hi Guys , I have a question : How to parallelize a FFT using C6678? I don´t want to use OMP Thank you for ReplyLopez
View ArticleForum Post: RE: Customer's I2C Question
Hi Sivaraj,The customer has come back with the following that they were able to get the system working. However there is some issues with the RRDY flag. Please help/advise:"All is working okay except I...
View ArticleForum Post: RE: Outbound Translation Region N Offset Configuration Issue Over...
In order to access those Application Registers in EP, RC will issue packets with PCIe addresses matching BAR0 of EP, and you access the OB_OFFSET_INDEX0 and OB_OFFSET_INDEX1 registers in EP with offset...
View ArticleForum Post: RE: FPGA to C6678 shared memory
Thank you Randy for your reply. I G bit/sec is my requirement.2 questions:1- Do we need a dedicated core to handle the PCIe TX/RX between the FPGA and the different cores?2- Does the FPGA need to sends...
View ArticleForum Post: RE: Fail to Receive ARP Request on PA_emacExample (C6670)
Aditya,The issue is related to Rx queue.In the L2/L3/L4 working case in PA,/* Setup the Rx queue as destination for the packets */rxQInfo =Qmss_getQueueNumber (gRxQHnd);queue = rxQInfo.qNum;flowId =...
View ArticleForum Post: RE: C6678 DDR3 initialization
Yes, it will start with step 1 of the initialization sequence. However, this does not capture all the initialization details since that is a JEDEC definition. Our DDR controller is JEDEC compatible so...
View ArticleForum Post: RE: What's the criteria for a valid boot image?
Hi Rahul,Were you able to learn anything from the information provided? Please let me know if you have any suggestions or need more informationthanks for your help!katrina
View ArticleForum Post: RE: C6678 cache problem
Si,When the document says L2/external, this means L2 SRAM or external RAM.[quote user="si cheng"]I am not clear that you say "writeback" means data is being written back if hit in L2 cache, Is the data...
View ArticleForum Post: RE: No API References for CCS, could anyone send me API Guide?...
Hi Kang,Have you checked the User Guide in the docs folder of DSPLIB 3.1.1 package. Click on the API reference link in that html page to look at description of APIs and their arguments. another option...
View ArticleForum Post: RE: C6747 - how to detect McASP AFIFO overrun / underrun
Pubesh,thanks for your hints. Yes, I know these sections, but in my experience this is not true when the AFIFO is in use. So when the AFIFO is in use, the XUNDRN and ROVRN bits will never ever get...
View ArticleForum Post: Syslink/RPMsg for Linux 3.2.x (dm816x)
Does somebody port Syslink 2.20 or another version to a newer kernel (e.g. 3.2.x), that in EZSDK one?As I understand it's better to use RPMsg (aka Syslink3) for it - may be it's already ported for 816x...
View ArticleForum Post: dvr_rdk SharedRegion_isCacheEnabled issue
Hi TI expertI use dvr_rdk 3.0 for our project, my hardware is custom dm8148 board and my video device connected to VIP1 POARTA , The video format is yuv422, 16bit, with discrete hsync and vsync.I am...
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