Si,
When the document says L2/external, this means L2 SRAM or external RAM.
[quote user="si cheng"]I am not clear that you say "writeback" means data is being written back if hit in L2 cache, Is the data being written back to L2 cache and then written back to external??[/quote]
If your question is specific to Section 4.3.8.3 Policy Relative to L1D Victims, which is what is quoted most recently, then the answer is "no". An L1D victim will only go to the L2 cache if it finds a hit in L2 cache.
This answer specifically applies to L1D victim traffic, which is different than most of your questions in this thread, which had to do with Block Coherence commands.
If you set L2 cache to 0, then it will be appropriate to use L1D coherence commands. If you set L2 cache to >0KB, then it will be appropriate to use L2 coherence commands, which will also handle all necessary L1D coherence operations.
If you set L2 cache to 32KB, you may not get any performance benefit from the L2 cache because of the interactions with L1D and L1P. I recommend either using more L2 cache or set L2 cache to 0KB. Please use testing and benchmarking to determine the effect on your performance, which may be very different than my recommendation.
Regards,
RandyP