Forum Post: C6678 Cache for L2SRAM

Hello

        These days when I run some applications on C6678, I check the memory browser in CCS,and find that some region in L2SRAM turns to grey,which means it been cached,and we find it's incoherenced!

        Does L2 and L1 keep cache coherence automaticlly?How can this happen？I‘m confused ,cay you explain the theory of this?

         And we learn that there is an XMC buffer between L2 and L3,can it cause the incoherence between the RAMs?

         Thank you very much.