Part Number: AM5728 Hi, I want to enable cache of the OCMC RAMs (DSP side). But according to the CorePac (sprugw0c) document, the OCMC RAMs region are in the shaded portion in the table that indicates MAR registers that are read-only. Are these OCMC RAMs cacheable? Please help me. Rishabh Garg in this thread is said that: "OCMC_RAM1 start address is 0x4030_0000 and size is 512 KB and hence cache will be enabled for full 0x4020_0000 to 0x4040_0000 region." Best regards, Omid
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