Hi Sivaraj K.
Thanks for your explanation most of that am I aware of. You might have some point on the ASM step and the DSP cycle some of the instructions takes up more cycles. To eliminate all the stall and wait state is a part of the optimization.
Let me then put my question another way.
Is it realistic to make a 300MHZ DSP running that kind of filter, 8 filter of 11 order and have additional 1 timer interrupt and a ADC sample interrupt on SPI , everything shall be finished within the 50us, further more there is also some kind of detection on the filter results that takes up what looks like a additional 1 filter (8*11).
The 8 filter use 64bit float point and have a total of 196 additions and 192 multiplication.
The code and arrays are all located in internal ram.
Claus.