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Forum Post: RE: About the priority of Cache_wb Cache_wbInvAll in C6657

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CheneyLiu,

Those are user coherence operations, and the Priority for those are set by the UCARBD and UCARBU registers (for L1D and L2 respectively.)  By default the UCARBx registers have the Priority set to 7.

More details on this and other Arbitration Registers can be found in section 8.3 of the C66 CorePac UG.

Best Regards,

Chad


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