[quote user="Joey Lin"]
I searched the spec, but I don't see where it has indicated how to
read locked data. My guess is that once I put data in cache, I just have to access the array address, and CPU will
check the cache for me.
[/quote]
Yes, locked cache entries work the same as normal unlocked cache entries. The only difference is that locking ensures it cannot be evicted (except by explicit cache maintainance operations).
[quote user="Joey Lin"]If my statement is right, how can I prove data is read from cache, not from RAM?[/quote]
There are many ways to detect whether an access is hitting cache or not. A side-effect of caching is loss of coherency: once a line is in cache, changes made by other masters will not be noticed by the cortex-a8, reads will continue to return the same cached data. You can test this by attempting to load a cache line (by accessing it or using the PLE) and then modifying memory through DMA or via JTAG (though DAP or any core other than the cortex-a8).
For write-back cacheable memory regions you get similar behaviour on writes: a write performed by the cortex-a8 would end up in cache and remain invisible to other masters until the cache line is evicted.
An alternative approach has already been mentioned above: configure the performance counters to measure various statistics on cache activity.
If cache doesn't seem to be working, then some things to check:
- Are bit 0 (MMU enabled) and bit 2 (data caching enabled) set in the control register?
- Is bit 2 (L2EN) set in the auxiliary control register?
- Is your memory region configured as cacheable and non-shareable?
Note that if the MMU is disabled then all memory regions are considered "strongly-ordered" and PLE operations will "complete" instantly without doing anything.