Forum Post: DM365 UBL_MAGIC_PLL and behavior of the PLL

I am trying to determine the behavior of the PLL when using UBL magic number UBL_MAGIC_PLL. I have modified the M and N values in the UBL descriptor, and I do see respective changes to the boot time. However, I would like to see how far I can push the PLL. For this, I need to determine exactly how the PLL is being configured. The ARM SoC RG is unclear, it says:

"When NAND boot mode is used with PLL option, ARM frequency is stepped up based on multiplier and

pre-divider values supplied in the UBL descriptor."

and

"AEMIF Clock (PLLC1SYCLK4)/2"

My best guess for how things work is:

PLLDIV4 = 1   (SYSCLK4 = PLL1CLK / 2)

PLLM = M   (multiplier is M + 1)

PREDIV = N    (divider is N + 1)

My testing seems to indicate that this is not quite the case!

Can someone with access to the ROM source code or familiar with how the PLL is initialized by the ROM provide comment???

Thanks!