Forum Post: C6472 - clarification on EDMA maxwait and SRIO DMA maxwait

Hi

This relates to a post on CPU vs SRIO priority to L2.  But in this case, its EDMA vs SRIO priority to DDR.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/254392/1182136.aspx#1182136

I'd like to know what register defines the EDMA MAXWAIT when SRIO is set to a higher priority in PER_SET_CTRL relative to the EDMA priority in QUEPRI. From what I've read, the EMCSDMAARBE register defines the SDMA MAXWAIT for SDMA access which is used be both the SRIO and EDMA to access DDR. So how do you define different MAXWAITs? 

Or is it the case that if SRIO has higher priority than the EDMA, the MAXWAIT in EMCSDMAARBE applies to EDMA? And if reversed, the MAXWAIT then applies to SRIO?

Reference: Bandwidth management Architecture. See Chapter 6 (p144) of C64x plus Megamodule spru871k.pdf

Cheers2u