Gregor,
0x840D vs 0x40D, the extra setting bit means PCIESSMODE as PCIE RC, this is latched to SW5 PIN 7 AND 8 of 6657 EVM, I don't know how they are set. I assume you have the code flashed to SPI NOR and put DSP in SPI boot mode to run, after running the code, why you need to use CCS debugger to load and run the same code? Just a trial?
For 0x305 for the PCIE_STS register, this should be fine.
Regards, Eric