Hi Akchurin,
I hope you’re using parallel way to interface image sensor module to DM6437,you need to use external crystal oscillator to generate 26.7MHz clock for SYSCLK input and connect the PIXCLK to VPBECLK on DM6737 device followed by Line Valid to HYSNC pin - An HSYNC indicates that one line of the frame is transmitted and Frame Valid to – VSYNC pin - This signal is often a way to indicate that one entire frame is transmitted.
Please refer the Aptina MT9D131 headboard schematics for more details file:///C:/Users/x0187392/Downloads/MT9D131_DemoHeadboard_C.pdf
Regards
Antony
--------------------------------------------------------------------------------------------------
Please click the Verify Answer button on this post if it answers your question.