Hello,
I had to change the clock buffers on my board design and just realized they don't have a high-z output mode, only a static differential "off" (P low, N high).
The datasheet specifies that the clocks must be high-z as the CVDD rail comes up, but since the clock inputs are AC/cap-coupled, is this really necessary?
I would simply change the part, but it is not convenient at this point.
Thanks
Tristan