I am planning on using the Serial RapidIO (SRIO) Peripheral of the C6657 (http://www.ti.com/product/tms320c6657). It is my understanding that its clock is set from the the SGMII PLL which is sourced by the SRIOSGMIICLK P/N (ball no AE13 and AE14 repectivly). In both the Hardware design guide (http://www.ti.com/lit/an/sprabi2c/sprabi2c.pdf ) or the clocking guide (http://www.ti.com/lit/an/sprabi4/sprabi4.pdf) I cannot find the jitter requirements. The jitter requirements are however listed for the CORECLK, and DDRCLK both of which I am also planning on using. I was wondering are the jitter requirements the same for the  SRIOSGMIICLK the same?

 It is my understanding that the CDCE62002 clock generator meets the requirements for the C6657. I am planning on using two CDCE62002 clock generators for the DDR and CORE PLL clock inputs. Since this part meets the requirements for the C6657 (http://www.ti.com/product/cdce62002) will it be suitable for the SRIOSGMIICLK also?