Forum Post: C6657 power on sequence clairification

I am using the I/O before core power on sequence in my design and have the following question.

Document SPRS814 has a note in section 7.2.1.2 where TI reccomends a maximum of 100ms between one rail and the next. My design is using a rather large FPGA to control the DSP power on sequence. In this case the 1.8 volt I/O rail will be powered on for ~1.5 seconds while the FPGA boots then CVDD, CVDD1 and the DDR3 1.5V rails will be sequenced on.

Is this going to be an issue?

David