Sam,
Is it correct that the ISR reads only 1 byte from the UART's receive FIFO and then returns from the ISR? And the DMA is not enabled in this case, right?
The fact that the ISR waits 200-300 us between interrupt events means that the problem is not in the EDMA3's setup or in the ISR's setup, since they were done independently and get the same results.
So there is something in the UART's operation that leads it to wait a long time to send out the next event. Maybe this is programmable - a delayed event trigger if there is more data in the FIFO.
I mentioned a method (untested) to generalize the process of using the EDMA3 efficiently (reading more than 1 byte at a time) with a timer-based poll for whether a message has completed. That discussion was in my first reply on this thread.
The best use of the EDMA3 is for reading data from the FIFO in chunks instead of just one-at-a-time. That conflicts with the need to have an unknown number of bytes in the message, and it conflicts with the efficiency of reading more than 1 byte when an event is sent to the DMA.
If you let the UART send an event to the DMA only when there are at least 8 bytes to be read, then your DMA operation will be efficient. When your timer-based polling routine checks and sees that there has been data read by the DMA, it can check the FIFO to see if there is any data there. The next time the routine comes around, if there has been no more data read and no new data in the FIFO, you may be able to assume the message is complete.
That was not a very involved explanation, but we can discuss it more if you are interested.
Your solution may be changing how often the UART repeats pending events. But that could be combined with the DMA change to make it all work well together.
Regards,
RandyP