Steve,
Sorry that I could not get back to you sooner. It might be better to start a new thread for different issue next time, that all the other community members could be notified and try to help as well.
The only major difference I can think of between L2 and MSMC SRAM is the cache configuration. I am not sure how the data flow is in your setup but if only EDMA receives from McBSP to device memory (the CPU does not touch the receiving data), then it should not matter it is L2 or MSMC. But you can still disable all the L1D and L2 cache in the beginning of your test to see if it matters.
For the data corruption, I am thinking it could be related to the clock/frame sync clock setup. Could you confirm the clock setup in your McBSP registers configuration and compare with McBSP user guide to see if they make sense please?
For your convenience, I list some bit fields below to check but it will be better to check all the other related ones in user guide as well:
(if you use external source for both data clock and frame sync clock)
DLB = 0 in SPCR (no loopback)
FSXM = FSRM = 0 in PCR (external source)
CLKXM = CLKRM = 0 in PCR (external source)
section 2.5.5.5 "In the case of a 0-bit data delay, the data must be ready for reception and/or transmission on the same serial clock cycle. For reception, this problem is solved by receive data being sampled on the first falling edge of CLKR when an active (high) FSR is detected"
RDATDLY = 0 in RCR (0-bit delay)
CLKRP = FSRP = 0 in PCR (falling edge, active high for receive)
Please also check the frame length and word length to match your receiving stream as well.