The project now does ping-pong DMA with codec receive and transmit, in both DSP and I2S modes, both mono and stereo. However in both mono and stereo it is only transmits the left channel. As before the I2STXRT0 and I2STXRT1 registers are always zeroed. The receive registers load properly in stereo and mono.
I am using the CSL but have copied the needed source files into the build directory so that I may try different memory models, pointer diff lengths. None of these efforts have made any difference.
I think my silicon is busted. To determine this I would like someone with an EZDSP5535 to configure the project for stereo, build and run, halt and examine the contents of the I2S2 registers mentioned above. I am hopeful that my problem is just another register setting somewhere.
Attached is a project for CCSv4. All tool versions and instructions are included in the readme.txt.