Hi Eric
Thank you for your answer,I have understanded what you said. So if we want to test the average rate of large size transfer(so we can ignore the latency from data going out of Tx to landing in target memory).
In this condition,if we start next EDMA immediately after last EDMA ending, can we make sure that there will be no corrupt?
If we count the whole time the transfer takes, then calculate rate by it.Does the result declare the transfer rate of the PCIE lane correctly?
Regards